ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 493

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Video Input Port Register Descriptions
6.10.2.7 VIP Task A Video Even Base Address (VIP_TASK_A_VID_EVEN_BASE)
VIP Memory Offset 18h
Type
Reset Value
6.10.2.8 VIP Task A Video Odd Base Address (VIP_TASK_A_VID_ODD_BASE)
VIP Memory Offset 1Ch
Type
Reset Value
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31:0
31:0
Bit
Bit
Name
TASK_A
VIDEO_EVEN
BASE
Name
TASK_A_VIDE
O_ODD_BASE
R/W
00000000h
R/W
00000000h
TASK_A_VIDEO_EVEN_BASE_ADDRESS
Description
Task A Video Even Base Address. This register specifies the base address in graphics
memory where Task A even video field data will be stored. Changes to this register take
effect at the beginning of the next field. This value needs to be 32-byte aligned. (Bits [4:0]
are required to be 00000.)
Note: This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Base Register Not Updated bit
(VIP Memory Offset 08h[16]) is set to 1. The Task A Video Data Even Base Address reg-
ister is not updated at this point. When the first data of the next field is captured, the
pending values of all base registers are written to the appropriate base registers, and the
Base Register Not Updated bit is cleared.
Description
Task A Video Odd Base Address. This register specifies the base address in graphics
memory where Task A odd video field data will be stored. Changes to this register take
effect at the beginning of the next field. This value needs to be 32-byte aligned. (Bits [4:0]
are required to be 00000.)
Note: This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Base Register Not Updated bit
(VIP Memory Offset 08h[16]) is set to 1. The Task A Video Data Odd Base Address Reg-
ister is not updated at this point. When the first data of the next field is captured, the
pending values of all base registers are written to the appropriate base registers, and the
Base Register Not Updated bit is cleared.
VIP_TASK_A_VID_EVEN_BASE Bit Descriptions
VIP_TASK_A_VID_ODD_BASE Bit Descriptions
VIP_TASK_A_VID_ODD_BASE Register Map
VIP_TASK_A_VID_EVEN_BASE Register Map
TASK_A_VIDEO_ODD_BASE
9
8
8
33234C
7
7
6
6
5
5
4
Program to 00000
4
Program to 00000
3
3
2
2
1
1
0
493
0