ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 368

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.19.24 Vertical Blank Start
Index
Type
Reset Value
6.6.19.25 Vertical Blank End
Index
Type
Reset Value
6.6.19.26 CRTC Mode Control
Index
Type
Reset Value
368
Bit
7:0
Bit
7:0
Bit
7
6
5
4
3
2
Name
V_BL_ST
Name
V_BL_END
Name
ENSYNC
BTMD
AW
RSVD
RSVD
VCKL_SL
15h
R/W
00h
16h
R/W
00h
17h
R/W
00h
33234C
Description
Vertical Blank Start Register Bits [7:0]. This is the low eight bits of a value that speci-
fies the starting scan line of the vertical blank signal. This is a 10-bit value. Bit 8 is in the
Overflow register (Index 07h[3] and bit 9 is in the Maximum Scan Line register (Index
09h[5].
Description
Vertical Blank End. This value specifies the low eight bits of a compare value that repre-
sents the scan line where the vertical blank signal goes inactive.
Description
Enable Syncs. When set to 1, this bit enables the horizontal and vertical sync signals.
When 0, this bit holds both sync flip-flops reset.
Byte Mode. If the DWORD mode bit (DW, Index 14h[6]) is 0, then this bit configures the
CRTC addresses for byte addresses when set to 1, or WORD addresses when set to 0. If
DW is set to 1, then this bit is ignored. See Table 6-55 on page 369 for information on the
various CRTC addressing modes.
Address Wrap. When the CRTC is addressing the frame buffer in Word Mode (Byte
Mode = 0, DWORD Mode = 0) then this bit determines which address bit occupies the
MA0 bit position of the address sent to the frame buffer memory. If Address Wrap = 0,
CRTC address counter bit 13 occupies the MA0 position. If Address Wrap = 1, then
CRTC address counter bit 15 is in the MA0 position. See Table 6-55 on page 369 for
information on the various CRTC addressing modes.
Reserved.
Not Implemented. (Count by 2)
VCLK Select. This bit determines the clocking for the vertical portion of the CRTC. If this
bit is 0, the horizontal sync signal clocks the vertical section. If this bit is 1, the horizontal
sync divided by two clocks the vertical section.
CRTC Mode Control Register Bit Descriptions
Vertical Blank Start Register Bit Descriptions
Vertical Blank End Register Bit Descriptions
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book