ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 197

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5.2.110 Memory Subsystem Array Control Enable MSR (MSS_ARRAY_CTL_EN_MSR)
MSR Address
Type
Reset Value
The MSRs at addresses 00001980h-00001983h provide alternate array delay control values for the MSS arrays. After a
reset, the MSS clock modules provide JTAG-accessible control values. These MSRs can be used by software to override
these values.
5.5.2.111 Memory Subsystem Array Control 0 MSR (MSS_ARRAY_CTL0_MSR)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:36
35:27
26:18
17:12
63:1
11:6
Bit
Bit
5:3
2:0
0
DMDATA1
Name
RSVD
EN
Name
RSVD
DMDATA1
DMDATA0
DMTAG1
DMTAG0
L2TB1
L2TB0
00001980h
R/W
00000000_00000000h
00001981h
R/W
00000000_2010F3C9h
DMDATA0
Description
Reserved. (Default = 0)
Enable. Enable the array control values in this register to be used instead of those pro-
vided by the clock modules.
0: Disable.
1: Enable.
Description
Reserved. (Default = 0)
Data Memory Subsystem Data 1 Delay Control. (Default = 04)
Data Memory Subsystem Data 0 Delay Control. (Default = 04)
Data Memory Subsystem Tag 1 Delay Control. (Default = F)
Data Memory Subsystem Tag 0 Delay Control. (Default = F)
Data Memory Subsystem L2 TLB 1 Delay Control. (Default = 1)
Data Memory Subsystem L2 TLB 0 Delay Control. (Default = 1)
MSS_ARRAY_CTL_EN_MSR Bit Descriptions
MSS_ARRAY_CTL_EN_MSR Register Map
MSS_ARRAY_CTL0_MSR Bit Descriptions
MSS_ARRAY_CTL0_MSR Register Map
RSVD
RSVD
RSVD
DMTAG1
DMTAG0
9
9
8
8
33234C
7
7
6
6
5
5
L2TLB1
4
4
3
3
DMDATA1
2
2
L2TLB0
1
1
197
EN
0
0