ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 327

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Display Controller Register Descriptions
6.6.5.3
DC Memory Offset 048h
Type
Reset Value
This register contains CRT horizontal sync timing information. Note however, that this register should also be programmed
appropriately for flat panel only display, since the horizontal sync transition determines when to advance the vertical
counter.
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:28
27:16
15:12
31:28
27:16
15:12
11:0
11:0
Bit
Bit
RSVD
DC CRT Horizontal Sync Timing (DC_H_SYNC_TIMING)
Name
RSVD
H_BLK_END
RSVD
H_BLK_START
Name
RSVD
H_SYNC_END
RSVD
H_SYNC_ST
R/W
xxxxxxxxh
H_SYNC_END
Description
Reserved. These bits should be programmed to zero.
Horizontal Blank End. This field represents the pixel clock count at which the horizontal
blanking signal becomes inactive minus 1.
Unlike previous versions of the DC, this field can be programmed to any pixel granularity;
it is not limited to character (8-pixel) granularity.
Reserved. These bits should be programmed to zero.
Horizontal Blank Start. This field represents the pixel clock count at which the horizon-
tal blanking signal becomes active minus 1.
Unlike previous versions of the DC, this field can be programmed to any pixel granularity;
it is not limited to character (8-pixel) granularity.
Description
Reserved. These bits should be programmed to zero.
Horizontal Sync End. This field represents the pixel clock count at which the CRT hori-
zontal sync signal becomes inactive minus 1.
Unlike previous versions of the DC, this field can be programmed to any pixel granularity;
it is not limited to character (8-pixel) granularity.
The horizontal sync must be at least 8 pixels in width.
Reserved. These bits should be programmed to zero.
Horizontal Sync Start. This field represents the pixel clock count at which the CRT hori-
zontal sync signal becomes active minus 1.
Unlike previous versions of the DC, this field can be programmed to any pixel granularity;
it is not limited to character (8-pixel) granularity.
The horizontal sync must be at least 8 pixels in width, and cannot begin until at least 8
pixels after H_BLK_START (DC Memory Offset 044h[11:0]).
DC_H_BLANK_TIMING Bit Descriptions
DC_H_SYNC_TIMING Bit Descriptions
DC_H_SYNC_TIMING Register Map
RSVD
9
8
33234C
7
H_SYNC_ST
6
5
4
3
2
1
327
0