ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 227

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Memory Controller Register Descriptions
6.2.2.10 Timing and Mode Program (MC_CF8F_DATA)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
2
1
0
CAS_LAT
STALE_REQ
Name
RSVD
SOFT_RST
PROG_DRAM
ACT2ACTREF
20000019h
R/W
18000008_287337A3h
Description
Reserved.
Software Reset. Puts the GLMC in a known state. Does not change configuration regis-
ters. The recommended sequence to use is:
1) Make sure SDRAM interface has “been idle for a while”.
2) Set software reset, then clear software reset.
3) Do a refresh cycle.
Accesses to memory may resume as normal following this.
Note that configuration registers are not scannable. To reproduce a problem in simulation
requires saving the configuration registers with software in silicon and reprogramming the
values in simulation. (Default = 0)
Program Mode Register in SDRAM. When this bit is set, the GLMC will issue one Load
Mode Register command to the DRAMs. It either programs the Mode Register (if
MSR_BA, bits [29:28] = 00), or the Extended Mode Register (if MSR_BA, bits [29:28] =
01). The Mode Register is programmed with CAS latency (see MSR 2000019h[30:28]),
wrap type sequential, and burst length of 4 for 64-bit data path, or burst length of 8 for 32-
bit wide data path. The Extended Mode Register in DDR DIMMs is programmed with the
QFC#, drive strength and DLL disable bits [26:24]. The Extended Mode Register must
be programmed first to enable the DLLs, then the Mode Register. This bit must be set
and cleared for each Load Mode Register command. (Default = 0)
RSVD
ACT2PRE
MC_CF07_DATA Bit Descriptions (Continued)
MC_CF8F_DATA Register Map
PRE2ACT
ACT2CMD
RSVD
ACT2ACT
9
8
33234C
7
6
RSVD
5
4
3
2
1
227
0