ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 543

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor Register Descriptions
6.14.2.3 Chip Fabrication Information (GLCP_FAB)
MSR Address
Type
Reset Value
This read only register is used to track various fab, process, and product family parameters. It is meant for AMD internal use
only. Reads reurn reset value.
6.14.2.4 GLCP Global Power Management Controls (GLCP_GLB_PM)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:18
15:13
Bit
7:5
2:1
17
16
12
11
10
9
8
4
3
0
Name
RSVD
DOTPLL_EN
SYSPLL_EN
RSVD
OUT_VP
OUT_GIO
OUT_GLMC
OUT_PCI
OUT_OTHER
RSVD
CLK_DLY_EN
CLK_DIS_EN
RSVD
THT_EN
4C00000Ah
RO
00000000_00000001h
4C00000Bh
R/W
00000000_00000000h
RSVD
Description
Reserved.
DOTPLL Enable. Enables turning off the Dot clock PLL during sleep when high.
SYSPLL Enable. Enables turning off the system PLLs during sleep when high.
Reserved.
VP Outputs. When set, enables VP outputs to TRI_STATE during a sleep sequence.
GIO Outputs. When set, enables Geode™ I/O comnpanion (GIO) to TRI_STATE device
outputs during a sleep sequence.
GLMC Outputs. When set, enables GLMC to TRI_STATE outputs during a sleep
sequence.
GLPCI Outputs. When set, enables GLPCI to TRI_STATE outputs during a sleep
sequence.
Other Outputs. When set, enables TDBGO and SUSPA# to TRI_STATE during a sleep
sequence.
Reserved.
Clock Delay Enable. Enables gating off clock enables from a delay rather than
GLCP_CLK4ACK (MSR 4C000013h) when high.
Clock Display Enable. Enables the assertion of internal signal, mb_clk_dis_req, during
a sleep sequence when high.
Reserved.
Throttle Enable. Enables processor throttling functions. If this bit is low, all the functions
related to throttling are disabled (GLCP_TH_OD, GLCP_CNT, etc.).
GLCP_GLB_PM Bit Descriptions
GLCP_GLB_PM Register Map
RSVD
RSVD
9
8
33234C
7
RSVD
6
5
4
3
2
1
543
0