ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 557

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor Register Descriptions
6.14.2.19 GLCP Throttle or C2 Start Delay (GLCP_TH_SD)
MSR Address
Type
Reset Value
6.14.2.20 GLCP Scale Factor (GLCP_TH_SF)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:13
11:0
63:8
Bit
Bit
7:0
12
Name
RSVD
P_LVL2_IN
THT_DELAY
Name
RSVD
SCALE
4C00001Ch
R/W - I/O Offset 10h
00000000_00000000h
4C00001Dh
R/W - I/O Offset 14h
00000000_00000000h
Description
Reserved. By convention, always write zero.
Enable Indicator. If P_LVL2 (in MSR 4C000019h) was read, then this bit reads high. If
this bit is written to a one, the suspend is aborted. This bit is always cleared and Suspend
de-asserted on NMI, IRQ, SSMI, ASMI, DMI, or system Sleep.
Throttle Delay. Indicates how long to wait before beginning the processor throttling pro-
cess as defined by MSR 4C000018h. The delay setting is multiplied by 16 to get the
number of PCI clock cycles to wait, thus setting THT_DELAY = 3 causes a wait of 48 PCI
clock cycles.
Description
Reserved. By convention, always write 0.
Scale Factor. This value is used in conjunction with CLK_VAL in the GLCP_CNT MSR
(4C000018h[3:0]). This value times CLK_VAL (or 15-CLK_VAL) indicates the number of
PCI clock cycles to wait during processor active (or suspend) periods. The setting is mul-
tiplied by 16 to get the number of PCI clock cycles per period, thus SCALE = 3 and
CLK_VAL = 5 will have the processor active for 240 PCI clocks and suspended for 480
PCI clocks.
RSVD
GLCP_TH_SD Bit Descriptions
GLCP_TH_SF Bit Descriptions
RSVD
GLCP_TH_SD Register Map
GLCP_TH_SF Register Map
RSVD
RSVD
9
9
8
8
33234C
7
7
THT_DELAY
6
6
5
5
SCALE
4
4
3
3
2
2
1
1
557
0
0