ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 335

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Display Controller Register Descriptions
6.6.7.4
DC Memory Offset 07Ch
Type
Reset Value
This register is provided to enable testability of the compressed line buffer (FIFO) RAM. Before it is accessed, the DIAG bit
should be set high (DC Memory Offset 004h[28] = 1) and the DFLE bit should be set low (DC Memory Offset 004h[0] = 0).
Also, the CFRW bit in DC_GENERAL_CFG (DC Memory Offset 004h[29]) should be set appropriately depending on
whether a series of reads or writes is to be performed. After each write, the FIFO write pointer automatically increments.
After all write operations are performed, the CFRW bit should be set high to enable read addresses to the FIFO and a pair
of reads of don't care data should be performed to load 64 bits of data into the output latch. Each subsequent read contains
the appropriate data that was previously written. After each pair of reads, the FIFO read pointer automatically increments.
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:0
Bit
DC Compression FIFO Diagnostic (DC_CFIFO_DIAG)
Name
CFIFO_DATA
R/W
xxxxxxxxh
Description
Compressed Data FIFO Diagnostic Read or Write Data.
DC_CFIFO_DIAG Bit Descriptions
DC_CFIFO_DIAG Register Map
CFIFO_DATA
9
8
33234C
7
6
5
4
3
2
1
335
0