ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 518

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.12.3.2 SB Control B (SB_CTL_B)
SB Memory Offset 004h
Type
Reset Value
518
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:8
Bit
7:6
5
4
3
2
1
0
Name
RSVD
RSVD
CBCB
SCB
DCB
WKB
ECB
STB
R/W
00000000h
33234C
Description
Reserved.
Reserved. These bits are implemented but reserved for future use. When writing to this
register, software should set these bits to 0 and ignore them on read.
Cipher Block Chaining (CBC) Mode for B Pointer. When set, the AES engine
encrypts/decrypts using the Cipher Block Chaining Mode for the B pointer. When reset,
the AES engine encrypts/decrypts using the Electronic Codebook (ECB) Mode. No ini-
tialization vector is used when in ECB mode.
Source Coherency for B Pointer Set. When set, the source memory fetches using the
GLIU interface are flagged as coherent operations. When reset, the operations are non-
coherent.
Destination Coherency for B Pointer Set. When set, the destination memory writes
using the GLIU interface are flagged as coherent operations. When reset, the operations
are non-coherent.
Writable Key for B Pointer Set. When set, the AES engine uses the key from the Writ-
able Key register (SB Memory Offset 030h-03Ch) for its next operation. When reset, it
uses the hidden key value.
Encrypt for B Pointer. When set, the AES operates in encryption mode. When reset, it
operates in decryption mode.
Start for B Pointer. When set, this bit commands the AES to start a new operation
based on the current control register setting and the settings in SB Memory Offset 020h
and 024h. This bit is reset automatically when the operation completes. Setting this bit
also clears the “Complete” flag in the AES Interrupt register (SB Memory Offset
008h[17]) and in the SB GLD SMI MSR (MSR 58002002h[33]). If an operation using the
A pointer set is already underway, the new operation for pointer set B will not start until
the previous A operation completes. If both A and B start bits are asserted in the same
write operation, the A operation take precedence.
SB_CTL_B Register Bit Descriptions
RSVD
SB_CTL_B Register Map
AMD Geode™ LX Processors Data Book
9
Security Block Register Descriptions
8
RSVD
7
6
5
4
3
2
1
0