ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 88

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.2
The CPU Core instruction set can be divided into nine
types of operations:
• Arithmetic
• Bit Manipulation
• Shift/Rotate
• String Manipulation
• Control Transfer
• Data Transfer
• Floating Point
• High-Level Language Support
• Operating System Support
The instructions operate on as few as zero operands and
as many as three operands. A NOP (no operation) instruc-
tion is an example of a zero-operand instruction. Two-oper-
and instructions allow the specification of an explicit source
and destination pair as part of the instruction. These two-
operand instructions can be divided into ten groups accord-
ing to operand types:
• Register to Register
• Register to Memory
• Memory to Register
• Memory to Memory
• Register to I/O
• I/O to Register
• Memory to I/O
• I/O to Memory
• Immediate Data to Register
• Immediate Data to Memory
An operand can be held in the instruction itself (as in the
case of an immediate operand), in one of the processor’s
registers or I/O ports, or in memory. An immediate operand
is fetched as part of the opcode for the instruction.
Operand lengths of 8, 16, 32 or 48 bits are supported as
well as 64 or 80 bits associated with floating-point instruc-
tions. Operand lengths of 8 or 32 bits are generally used
when executing code written for 386- or 486-class (32-bit
code) processors. Operand lengths of 8 or 16 bits are gen-
erally used when executing existing 8086 or 80286 code
(16-bit code). The default length of an operand can be
overridden by placing one or more instruction prefixes in
front of the opcode. For example, the use of prefixes allows
a 32-bit operand to be used with 16-bit code or a 16-bit
operand to be used with 32-bit code.
88
Instruction Set Overview
33234C
The Processor Core Instruction Set (see Table 8-26 on
page 628) contains the clock count table that lists each
instruction in the CPU instruction set. Included in the table
are the associated opcodes, execution clock counts, and
effects on the EFLAGS register.
5.2.1
The LOCK prefix may be placed before certain instructions
that read, modify, then write back to memory. The PCI will
not be granted access in the middle of locked instructions.
The LOCK prefix can be used with the following instructions
only when the result is a write operation to memory.
• Bit Test Instructions (BTS, BTR, BTC)
• Exchange Instructions (XADD, XCHG, CMPXCHG)
• One-Operand Arithmetic and Logical Instructions (DEC,
• Two-Operand Arithmetic and Logical Instructions (ADC,
An invalid opcode exception is generated if the LOCK pre-
fix is used with any other instruction or with one of the
instructions above when no write operation to memory
occurs (for example, when the destination is a register).
5.2.2
The accessible registers in the processor are grouped into
two sets:
1)
2)
Both of these register sets are discussed in detail in the
subsections that follow.
INC, NEG, NOT)
ADD, AND, OR, SBB, SUB, XOR).
The Application Register Set contains the registers
frequently used by application programmers. Table 5-2
on page 89 shows the General Purpose, Segment,
Instruction Pointer and EFLAGS registers.
The System Register Set contains the registers typi-
cally reserved for operating systems programmers:
Control, System Address, Debug, Configuration, and
Test registers. All accesses to the these registers use
special CPU instructions.
Lock Prefix
Register Sets
AMD Geode™ LX Processors Data Book
CPU Core