ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 150

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.5.2.52 Instruction Cache Index MSR (IC_INDEX_MSR)
MSR Address
Type
Reset Value
5.5.2.53 Instruction Cache Data MSR (IC_DATA_MSR)
MSR Address
Type
Reset Value
150
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:18
17:16
15:11
10:7
63:0
Bits
Bits
6:0
Name
RSVD (RO)
DSEL
RSVD (RO)
WAY
LINE
Name
DATA
00001710h
R/W
00000000_00000000h
00001711h
R/W
xxxxxxxx_xxxxxxxxh
33234C
RSVD
Description
Reserved (Read Only).
Data QWORD Select for L1 Cache MSR Access. Determines which QWORD in a
cache line is accessed by a read or a write to IC_DATA_MSR (MSR 00001711h). This
field resets to 0 on any access to IC_TAG_MSR (MSR 00001712h) or IC_TAG_I_MSR
(MSR 00001713h) and increments on access to IC_DATA_MSR. This field is not used
when accessing the L0 cache. (Default = 0)
Reserved (Read Only).
L1 Cache Way to Access. Forms the high-order bits of an 11-bit counter. The LINE field
(bits [6:0]) forms the low seven bits of the counter. This field increments when the LINE
field overflows on a access to IC_TAG_I_MSR (MSR 00001713h). This field is not used
for the L0 cache. (Default = 0)
L1 Cache Line to Access. Forms the low-order bits of an 11-bit counter. The WAY field
(bits [3:0]) forms the high four bits of the counter. This field post-increments on an access
to IC_TAG_I_MSR (MSR 00001713h). When accessing the L0 cache, only bits [4:0] are
important and are used to select the line to read in the L0 cache. (Default = 0)
Description
QWORD to Read from or Write to the L1 Cache. The address to the QWORD specified
by the LINE and DSEL fields from IC_INDEX_MSR (MSR 00001710h). The way in the
cache to read and write is specified by the WAY field in IC_INDEX_MSR. Each access to
IC_DATA_MSR increments DSEL.
IC_INDEX_MSR Bit Descriptions
IC_DATA_MSR Bit Descriptions
IC_INDEX_MSR Register Map
IC_DATA_MSR Register Map
DSEL
DATA (Upper)
DATA (Lower)
RSVD
RSVD
AMD Geode™ LX Processors Data Book
9
9
WAY
8
8
CPU Core Register Descriptions
7
7
6
6
5
5
4
4
LINE
3
3
2
2
1
1
0
0