ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 421

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Video Processor Register Descriptions
AMD Geode™ LX Processors Data Book
16:14
13:10
Bit
7:6
5:4
9
8
3
2
1
0
Name
CRT_SYNC
_SKW
SP
CRT_VSYNC
_POL
CRT_HSYNC
_POL
RSVD (RO)
SP
DAC_BL_EN
VSYNC_EN
HSYNC_EN
CRT_EN
Description
CRT Sync Skew. Represents the number of pixel clocks to skew the horizontal and ver-
tical sync that are sent to the CRT. This field should be programmed to 100 (i.e., baseline
sync is not moved) as the baseline. Via this register, the sync can be moved forward
(later) or backward (earlier) relative to the pixel data. This register can be used to com-
pensate for possible delay of pixel data being processed via the Video Processor.
000: Sync moved 4 clocks backward.
001: Sync moved 3 clocks backward.
010: Sync moved 2 clocks backward.
011: Sync moved 1 clock backward.
100: Baseline sync is not moved. (Default)
101: Sync moved 1 clock forward.
110: Sync moved 2 clocks forward.
111: Sync moved 3 clocks forward.
Spares. Bits are read/write, but have no function.
CRT Vertical Synchronization Polarity. Selects the polarity for CRT vertical sync.
0: CRT vertical sync is normally low and is set high during the sync interval.
1: CRT vertical sync is normally high and is set low during the sync interval
CRT Horizontal Synchronization Polarity. Selects the polarity for CRT horizontal sync.
0: CRT horizontal sync is normally low and is set high during sync interval.
1: CRT horizontal sync is normally high and is set low during sync interval.
Reserved (Read Only). Reads back as 0.
Spares. Bits are read/write, but have no function.
DAC Blank Enable. Controls blanking of the CRT DACs.
0: DACs are constantly blanked.
1: DACs are blanked normally (i.e., during horizontal and vertical blank).
CRT Vertical Sync Enable. Enables/disables CRT vertical sync (used for VESA DPMS
support).
0: Disable.
1: Enable.
CRT Horizontal Sync Enable. Enables/disables CRT horizontal sync (used for VESA
DPMS support).
0: Disable.
1: Enable.
CRT Enable. Enables the graphics display control logic. This bit is also used to reset the
display logic.
0: Reset display control logic.
1: Enable display control logic.
DCFG Bit Descriptions (Continued)
33234C
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