ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 127

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5.2.21 Debug Management Interrupt (DMI) Control Register
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:10
Bit
9
8
7
6
5
4
3
2
Name
RSVD
DMI_TF
DMI_STALL
DMM_SUSP
DMI_TSS
DMM_CACHE
DMI_ICEBP
DMI_DBG
DMI_EXT
00001302h
R/W
00000000_00000000h
Description
Reserved. Write as read.
DMI Trap Flag.
0: Disable DMI single stepping.
1: If DMI_STALL (bit 8) is 0, DMI occurs after the successful execution of each instruc-
DMI Stall.
0: If not in DMM, DMI conditions cause DMIs.
1: DMI conditions cause a debug stall.
Enable SUSP# during DMM. Enable SUSP# during DMM mode.
0: Disable.
1: Enable.
Task Switch Debug Fault Control.
0: Task switch debug faults cause debug exceptions.
1: Task switch debug exceptions cause DMIs when not in DMM.
Cache Control during DMM.
0: Do not change CR0 CD and NW bits when entering DMM.
1: Set CR0, CD and NW bits when entering DMM
See Table 5-10 "CR0 Bit Descriptions" on page 94 for CD and NW bit descriptions.
Enable DMIs on ICEBP (F1) Instructions.
0: Disable.
1: Enable.
Enable Replacing Debug Exceptions as DMIs.
0: Disable.
1: Enable.
Enable External TDBGI Pin. Enable DMIs caused by the TDBGI pin (ball AB2) when not
in DMM.
0: Disable.
1: Enable.
tion. If DMI_STALL is 1, debug stall occurs after the successful execution of each
instruction.
DMI Control Register Bit Descriptions
RSVD
DMI Control Register Map
RSVD
.
9
8
33234C
7
6
5
4
3
2
1
127
0