ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 109

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5.2.3
MSR Address
Type
Reset Value
5.5.2.4
MSR Address
Type
Reset Value
SYS_CS_MSR is used by the SYSENTER instruction (fast system call) as the selector of the most privileged code seg-
ment. SYS_CS plus 8 is used by SYSENTER as the selector of the most privileged stack segment. SYS_CS plus 16 is
used by SYSEXIT as the selector of the least privileged code segment. SYS_CS plus 24 is used by SYSEXIT as the selec-
tor of the least privileged stack segment.
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
G
63:40
63:32
29:24
22:21
39:0
Bit
Bit
31
30
23
20
19
18
D
Performance Event Counter 1 MSR (PERF_CNT1_MSR)
SYSENTER/SYSEXIT Code Segment Selector MSR (SYS_CS_MSR)
Name
RSVD
PERF_CNT1
Name
RSVD
G (RO)
D (RO)
RSVD (RO)
P (RO)
DPL (RO)
S (RO)
X (RO)
C (RO)
RSVD
000000C2h
R/W
00000000_00000000h
00000174h
R/W
00000000_C09B0000h
P
Description
Reserved. Write as read.
Performance Event Counter 1. This register is a 40-bit event counter used to count
events or conditions inside the CPU Core. This counter is controlled by Performance
Event Counter 1 Select MSR (MSR 00000187h).
Description
Reserved.
Granularity (Read Only). Code segment limit granularity is 4 KB. (Default = 1)
Default (Read Only). Code segment default size is 32 bits. (Default = 1)
Reserved (Read Only).
Present (Read Only). Code segment descriptor is present. (Default = 1)
Descriptor Privilege Level (Read Only). Code segment descriptor privilege level.
(Default = 11)
Segment (Read Only). Code segment is not a system segment. (Default = 1)
Executable (Read Only). Code segment is executable. (Default = 1)
Conforming (Read Only). Code segment is conforming. (Default = 0)
DPL
PERF_CNT1_MSR Bit Descriptions
PERF_CNT1_MSR Register Map
SYS_CS_MSR Bit Descriptions
RSVD
S
SYS_CS_MSR Register Map
X
PERF_CNT1 (Low DWORD)
C
R
RSVD
A
CS_SEL
9
9
8
8
33234C
7
7
PERF_CNT1 (High Byte)
6
6
5
5
4
4
3
3
TI
2
2
1
1
RPL
109
0
0