ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 505

no-image

ALXD800EEXJ2VD

Manufacturer Part Number
ALXD800EEXJ2VD
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of ALXD800EEXJ2VD

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ALXD800EEXJ2VD
Manufacturer:
AMD
Quantity:
453
Part Number:
ALXD800EEXJ2VD
Manufacturer:
AMD
Quantity:
784
Part Number:
ALXD800EEXJ2VD
Manufacturer:
AMD
Quantity:
20 000
Company:
Part Number:
ALXD800EEXJ2VD C3
Quantity:
91
Part Number:
ALXD800EEXJ2VD-C3
Manufacturer:
INTEL
Quantity:
472
Part Number:
ALXD800EEXJ2VD-C3
Manufacturer:
AMD
Quantity:
20 000
Video Input Port Register Descriptions
6.10.2.28 VIP FIFO Data (VIP_FIFO_DATA)
VIP Memory Offset 74h
Type
Reset Value
6.10.2.29 VIP VSYNC Error Count (VIP_SYNC_ERR_COUNT)
VIP Memory Offset 78h
Type
Reset Value
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:24
31:0
23:0
Bit
Bit
VERTICAL_WINDOW
Name
FIFO_DATA
Name
VERTICAL_
WINDOW
VERTICAL_
COUNT
R/W
xxxxxxxxh
R/W
00000000h
Description
FIFO Data. When the FF_R/W bit is set (VIP Memory Offset 04h)[24] = 1), data written to
this register is stored in FIFO_ADDR (VIP Memory Offset 70h[7:0]). When the FF_R/W
bit is reset, data from the FIFO corresponding to the address in the FIFO_ADDR is
returned
Description
Vertical Window. This field defines the number of VIP clocks the input VBLANK can
vary before it is considered invalid. (16-4095 clocks)
Vertical Count. This field provides the check point for verifying that the input data stream
is maintaining consistent VSYNC timing. This count is the minimum number of VIP clocks
expected in an input field (interlaced video) or frame (non-interlaced video). If the number
of video clocks between rising edges of VBLANK is less then this number (or greater
then VERTICAL_COUNT + VERTICAL_WINDOW), a VSYNC error interrupt is gener-
ated and the video_ok output signal is forced low indicating invalid input video. (0-
16,777,215 clocks)
Note: A 60 Hz VBLANK rate @75 MHz input clock = 1,250,000 clocks.
VIP_SYNC_ERR_COUNT Bit Descriptions
VIP_SYNC_ERR_COUNT Register Map
VIP_FIFO_DATA Bit Descriptions
VIP_FIFO_DATA Register Map
FIFO_DATA
VERTICAL_COUNT
9
9
8
8
33234C
7
7
6
6
5
5
4
4
3
3
2
2
1
1
505
0
0

Related parts for ALXD800EEXJ2VD