ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 220

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.2.1.5
MSR Address
Type
Reset Value
6.2.1.6
MSR Address
Type
Reset Value
This register is reserved for internal use by AMD and should not be written to.
220
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:32
31:3
Bit
2
1
0
GLD Power Management (GLD_MSR_PM)
GLD Diagnostic (GLD_MSR_DIAG)
Name
RSVD (RO)
RSVD
PM1
RSVD
PM0
20002004h
R/W
00000000_00000000h
20002005h
R/W
00000000_00000000h
33234C
Description
Reserved (Read Only). Reads back 0s.
Reserved.
Power Mode 1. Clock gating for clock domains 0 (GLIU clock) and 1 (GLMC clock). Once
the GLMC becomes idle, it enters PMode1 by 1) closing all banks with a ‘precharge all’
command to the DIMMs, 2) issuing a self-refresh command, 3) bringing CKE1 and CKE0
(balls F4 and E4 respectively) low and putting the address and control pins in TRI_STATE
mode, and 4) shutting off its GLIU and GLMC clocks on the next clock after the self-
refresh. The GLMC resumes to full power after any activity is detected (i.e., a GLIU
request after reset).
0: Disable clock gating. Clocks are always ON. (Default)
1: Enable active hardware clock gating.
Reserved.
Power Mode 0. Clock gating for clock domain 0 (GLIU clock). Once the GLMC becomes
idle, it enters PMode0 by 1) bringing CKE1 and CKE0 (balls F4 and E4 respectively) low
and putting the address and control pins in TRI_STATE mode, then 2) shutting off its
GLIU clock on the next cycle. Its GLMC clock remains on to maintain the refresh
counters, as do the SDRAM clocks. The GLMC resumes full power either after any activ-
ity is detected, or when it needs to perform a refresh. The CKE pins are driven back high
and address/control pins driven back to their neutral states one cycle before the GLIU
clock is turned back on.
0: Disable clock gating. Clocks are always ON. (Default)
1: Enable active hardware clock gating.
GLD_MSR_PM Bit Descriptions
GLD_MSR_PM Register Map
RSVD
RSVD
GeodeLink™ Memory Controller Register Descriptions
AMD Geode™ LX Processors Data Book
9
8
7
6
5
4
3
2
1
0