ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 627

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Instruction Set
8.3
The instruction set for the Geode LX processor core is summarized in Table 8-26. The table uses several symbols and
abbreviations that are described next and listed in Table 8-25.
8.3.1
Opcodes are given as hex values except when they appear within brackets as binary values.
8.3.2
The clock counts listed in the instruction set summary table (Table 8-26) are grouped by operating mode (real and pro-
tected) and whether there is a register/cache hit or a cache miss. In some cases, more than one clock count is shown in a
column for a given instruction, or a variable is used in the clock count.
8.3.3
There are nine flags that are affected by the execution of instructions. The flag names have been abbreviated and various con-
ventions used to indicate what effect the instruction has on the particular flag.
AMD Geode™ LX Processors Data Book
Opcode
Clock Count
Flags
Abbreviation
Symbol or
+++
###
OF
DF
CF
TF
SF
ZF
AF
PF
##
IF
#
+
n
L
0
1
u
x
/
\
-
|
Processor Core Instruction Set
Opcodes
Clock Counts
Flags
Description
Immediate 8-bit data.
Immediate 16-bit data.
Full immediate 32-bit data (8, 16, or 32 bits).
8-bit signed displacement.
Full signed displacement (16 or 32 bits).
Register operand/memory operand.
Number of times operation is repeated.
Level of the stack frame.
Conditional jump taken | Conditional jump not taken. (e.g., “4|1” = four clocks if jump taken, one clock
if jump not taken).
CPL ≤ IOPL \ CPL > IOPL (where CPL = Current Privilege Level, IOPL = I/O Privilege Level).
Overflow Flag.
Direction Flag.
Interrupt Enable Flag.
Trap Flag.
Sign Flag.
Zero Flag.
Auxiliary Flag.
Parity Flag.
Carry Flag.
Flag is modified by the instruction.
Flag is not changed by the instruction.
Flag is reset to “0.”
Flag is set to “1.”
Flag is undefined following execution of the instruction.
Table 8-25. Processor Core Instruction Set Table Legend
33234C
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