ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 417

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Video Processor Register Descriptions
6.8.2
6.8.2.1
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:32
29:28
27:20
18:16
15:0
Bit
31
30
19
Video Processor Module Specific MSRs
VP Diagnostic MSR (MSR_DIAG_VP)
SM
RSVD
CM
NDM
SM
DVAL
D
RSVD
SP
Name
48000010h
R/W
00000000_00000000h
DVAL
Description
Reserved.
32-Bit CRC Mode. Selects 32-bit CRC generation.
0: Disable.
1: Enable.
New Dither Mode. Selects either the legacy dither mode, or new dither mode.
The legacy dither mode has an errata with the first pixel. The new dither mode fixes this
errata. This bit provided for backward compatibility.
0: Legacy dither mode.
1: New dither mode.
Sim Mode. This field is used to put the VP in modes to aid verification.
00: Normal operation.
01: Graphics input bypasses VP and goes directly to FP.
10: Reserved.
11: Reserved.
DAC Test Value. 8-bit data value to drive to CRT DAC when selected by bit 19. Dupli-
cate copies of DAC Test Value are driven on DAC RGB.
crt_dac_r[7:0] = DAC Test Value[7:0] (27:20 is this register)
crt_dac_g[7:0] = DAC Test Value[7:0] (27:20 is this register)
crt_dac_b[7:0] = DAC Test Value[7:0] (27:20 is this register)
To enable DAC Test Value to be driven to CRT DAC:
(DAC Test Value Select must = 0) AND
DAC Test Value Select. Selects which data stream is sent to CRT DAC during CRT
DAC test mode.
0: 24-bit data to CRT DAC = {3{DAC Test Value[27:20]}} (3 time repeated 8-bit value).
1: 24-bit data to CRT DAC = gfx_data[23:0] (raw input from display controller).
Reserved. Reserved for test purposes. Set to 000 for normal operation.
Spares. Read/write, no function.
((VTM[6] = 0 AND MBD_MSR_DIAG[18:16] = 101h) OR
(VTM[6] = 1 AND VTM[3:0] = 0001)h
MSR_DIAG_VP Bit Descriptions
MSR_DIAG_VP Register Map
D
TSEL
RSVD
9
8
SP
33234C
7
6
5
4
3
2
1
417
0