ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 553

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor Register Descriptions
6.14.2.14 GLCP Dot Clock PLL Control (GLCP_DOTPLL)
MSR Address
Type
Reset Value
This register does not include hardware handshake controls like the GLCP_SYS_RSTPLL register (MSR 4C000014h), so
care should be taken when changing the settings. For example, to change the DIV settings: write the register with the DOT-
RESET bit (bit 0) set and either in the same write or another write change the DIV settings; read the register until the LOCK
bit (bit 25) goes active (or until a timeout occurs, if desired); write the register with the same DIV settings and with the DOT-
RESET bit clear. The MDIV, NDIV, and PDIV (bits 46:32) settings work in conjunction to create the internal DOTCLK using
this equation:
For example, with bits [46:32] in the GLCP_DOTPLL register set to 0x00D7 (reset), the Dot clock frequency that the DC and
VP would run with would be:
However, not all MDIV, NDIV, and PDIV settings lock and not all that lock have good long-term jitter characteristics. The PLL
resets to 25.0565 MHz for VGA monitors assuming a 14.31818 MHz input. A 27 MHz input will successfully lock at about 47
MHz, and should then be changed to the desired pixel rate.
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
{PW1,IRQ13,PW0,SUSPA#,GNT#[2:0]}
same as GLCP_SYS_RSTPLL[7:1]
Table 6-88. Bootstrap Bit Settings and Reset State of GLCP_SYS_RSTPLL (PW1 and IRQ13 vary)
SWFLAGS
0100000
1000001
1110111
4C000015h
R/W
000000D7_02000000h
RSVD
Fout
=
Fout
14.318MHz
RSVD
=
GLCP_DOTPLL Register Map
Bypass
Speed
CPU
Fin
166
500
⋅
---------------------------------------------------------------
(
⋅
MDIV
----------------------------------
(
0
CORE
MULT
+
(
11
14
4
13
1
(
) 7
NDIV
+
+
(
1
1
)
+
MDIV
)
Bypass
Speed
⋅
GLIU
1
166
400
(
+
)
PDIV
1
=
RSVD
)
25.0565MHz
+
MULT
GLIU
1
11
7
4
)
9
8
NDIV
33234C
7
000005DD_030000EEh
00000396_00001840h
00000249_03000082h
GLCP_SYS_RSTPLL
6
RSVD
Reset Value
5
4
3
2
PDIV
1
553
0