ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 291
ALXD800EEXJ2VD
Manufacturer Part Number
ALXD800EEXJ2VD
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJ2VD.pdf
(675 pages)
Specifications of ALXD800EEXJ2VD
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Display Controller
6.5.6
The DC incorporates a 3x5 tap filter to be used for up/
downscaling of the graphics image. In order to support the
filter, three lines of buffering are also included. These three
line buffers support a frame buffer resolution of up to 1024
pixels wide. For wider images, the buffers are automatically
reconfigured into one line, and scaling is not supported. For
frame buffer images up to and including 1024 pixels in
width, vertical downscaling of up to (but not including) 2:1
is supported and horizontal downscaling of up to (but not
including) 2:1 is supported.
The filter is organized as five 3-tap vertical filters that feed
the five taps of a horizontal filter. The filter supports 1/256
inter-pixel quantization (i.e., 256-phase) in both the hori-
zontal and vertical directions. The filter coefficients are 10
bits wide.
AMD Geode™ LX Processors Data Book
Graphics Scaler/Filter
H Phase
H Phase Adder
Address
Line Buffer
Line Buffer
Line Buffer
V Phase
Line buffer selection
and routing
Address for H.
Coefficient RAM
Figure 6-20. Graphics Filter Block Diagram
V Phase Adder
Scaling is controlled by adjusting the horizontal and vertical
filter scale factors (through configuration register 90).
These numbers represent binary rational numbers in a
2.14 format. At the start of each frame, the H Phase Adder
and V Phase Adder are reset to 0. At the start of each scan
line, the V Phase adder is added to V Phase and the result
is stored in V Phase Adder. The integer portion of the value
in V Phase Adder indicates on which line the filter kernel is
centered. The most significant eight bits of the fractional
portion of this value determine the vertical phase for the
purpose of determining the filter coefficients.
The H Phase Adder mechanism is similar but operates on
pixels instead of lines.
A block diagram of the filter is shown in Figure 6-20.
V. Coefficient RAM
Address
X
X
X
33234C
+
To
horizontal
latches
291
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