ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 516

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

516
Bit
1:0
3
2
Name
SBY
SBI
DIV
33234C
Description
Swap Bytes. This bit controls a byte-swapping feature within the AES module. When
set, the bytes within the 16-byte block are swapped on both AES DMA reads and writes.
Byte 15 is swapped with byte 0, byte 14 is swapped with byte 1, etc. Asserting this bit
does not affect the slave operations to AES registers, (including the writable key), nor
does it affect EEPROM operations. When this bit is cleared, the DMA operations read
and write bytes with the same byte order as they appear in memory.
Swap Bits. This bit controls a bit-swapping feature within the AES module. When set,
the bits within each byte are swapped on both AES DMA reads and writes. Bit 7 is
swapped with bit 0, bit 6 is swapped with 1, etc. Asserting this bit does not affect the
slave operations to AES registers, (including the writable key), nor does it affect
EEPROM operations. When this bit is cleared, the DMA operations read and write bytes
with the same bit order as they appear in memory.
AES Enable Divider. These two bits control the ratio between the GLIU clock frequency
and the updating of the AES encryption engine registers. The AES module is clocked at
the GLIU frequency, however, the state registers only update on an enable pulse that
occurs each n cycles, where n is determined by the DIV value. This register should not
be changed during an AES operation.
00: Divide by 1 (use for 100 MHz GLIU or less).
01: Divide by 2 (use for 100 MHz to 200 MHz GLIU).
10: Divide by 3 (use for 200 MHz to 300 MHz GLIU).
11: Divide by 4 (use for 300 MHz to 400 MHz GLIU).
GLD_MSR_CTRL Bit Descriptions (Continued)
AMD Geode™ LX Processors Data Book
Security Block Register Descriptions