ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 538

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.14.1.3 GLD SMI MSR (GLD_MSR_SMI)
MSR Address
Type
Reset Value
538
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:21
15:5
Bit
20
19
18
17
16
4
3
2
1
0
Name
RSVD
SMI_EXT
SMI_PML2
SMI_PMCNT
SMI_DBG
SMI_ERR
RSVD
SMI_EXT_MASK
SMI_PML2_MASK
SMI_PMCNT_MASK
SMI_DBG_MASK
SMI_ERR_MASK
RSVD
4C002002h
R/W
00000000_0000001Fh
33234C
Description
Reserved.
SMI from I/O Companion. ASMI generated when most recent serial packet had
SMI bit set. This bit ALWAYS represents the state of the SMI bit in the last serial
packet received. It cannot be written. To clear external SMI sources, proper external
controls must be sent (i.e., via the PCI bus).
SMI Power Management GLCP_LVL2. SSMI generated when GLCP_LVL2 (MSR
4C000019h) I/O register was read. Write 1 to clear, 0 has no effect.
SMI Power Management GLCP_CNT Mask. SSMI generated when GLCP_CNT
(MSR 4C000018h) I/O register was written. Write 1 to clear, 0 has no effect.
SMI Debug. ASMI generated due to debug event or PROCSTAT access. Write 1 to
clear, 0 has no effect.
SMI Error. ASMI generated due to error signal. Write 1 to clear, 0 has no effect.
Reserved.
SMI from I/O Companion Mask. If clear, enables serial packets from external
device to generate an ASMI.
SMI Power Management GLCP_LVL2 Mask. If clear, enables power management
logic to generate an SSMI when GLCP_LVL2 I/O register (MSR 4C000019h) is
read.
SMI Power Management GLCP_CNT Mask. If clear, enables power management
logic to generate an SSMI when GLCP_CNT (MSR 4C000018h) I/O register is writ-
ten.
SMI Debug Mask. If clear, enables debug logic to generate an ASMI.
SMI Error Mask. If clear, then any GLIU device error signal (including GLCP)
causes an ASMI.
GLD_MSR_SMI Bit Descriptions
GLD_MSR_SMI Register Map
RSVD
GeodeLink™ Control Processor Register Descriptions
RSVD
AMD Geode™ LX Processors Data Book
9
8
7
6
5
4
3
2
1
0