ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 353

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Display Controller Register Descriptions
6.6.16
6.6.16.1 VGA Configuration (VGA_CONFIG)
DC Memory Offset 100h
Type
Reset Value
This register controls palette write operations.
6.6.16.2 VGA Status (VGA_STATUS)
DC Memory Offset 104h
Type
Reset Value
This register provides status information for the individual SMI events enabled in the VGA_CONFIG register (DC Memory
Offset 100h), as well as certain other status bits. Reading this register clears all active events.
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD
31:30
29:24
23:22
21:12
31:1
11:6
Bit
Bit
0
5
4
3
VGA Block Configuration Registers
Name
RSVD
WPPAL
Name
RSVD
BLINK_CNT
RSVD
V_CNT
RSVD
VSYNC
DISPEN
CRTCIO_SMI
BLINK_CNT
R/W
00000000h
RO
00000000h
RSVD
Description
Reserved. Set to 0.
Write Protect Palette. If set to 1, VGA palette write operations are NOT written to the
palette RAMs. Palette writes behave normally, except that the data is discarded.
Description
Reserved.
Blink Counter Value. Unsynchronized, used as a simulation aid.
Reserved.
Vertical Counter Value. Unsynchronized, used as a simulation aid.
Reserved.
VSYNC. 1 If VSYNC is active (copy of bit 3 of ISR1).
Display Enable. 0 if both horizontal and vertical display enable are active (copy of bit 0
of ISR1).
CRTC Register SMI. If = 1, an SMI was generated due to an I/O read or write to an non-
implemented CRTC register.
VGA_CONFIG Bit Descriptions
VGA_STATUS Bit Descriptions
VGA_CONFIG Register Map
VGA_STATUS Register Map
V_CNT
RSVD
RSVD
9
9
8
8
33234C
7
7
6
6
5
5
4
4
3
3
2
2
1
1
353
0
0