ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 573

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ PCI Bridge Register Descriptions
6.16.1.4 GLD Error MSR (GLD_MSR_ERROR)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:22
15:6
Bit
21
20
19
18
17
16
5
4
3
2
1
0
Name
RSVD (RO)
PARE
SYSE
RSVD (RO)
BME
TARE
MARE
RSVD (RO)
PARM
SYSM
RSVD (RO)
BMM
TARM
MARM
RSVD
50002003h
R/W
00000000_0000003Fh
Description
Reserved (Read Only). Reserved for future use.
Parity Error Event (Read/Write-1-to-Clear). This bit is asserted due to detection of a
PCI bus parity error. Write 1 to clear. PE (MSR 50002010h[31]) must be set to enable this
event. The event causes an ERR if PARM (bit 5) is cleared.
System Error Event (Read/Write-1-to-Clear). This bit is asserted due to the detection
of a PCI bus system error. Write 1 to clear. PE (MSR 50002010h[31]) must be set to
enable this event. The event causes an ERR if SYSM (bit 4) is cleared.
Reserved (Read Only). Reserved for future use.
Broken Master Event (Read/Write-1-to-Clear). This bit is asserted due to detection of a
broken PCI bus master. Write 1 to clear. BME (MSR 50002010h[30]) must be set to
enable this event. The event causes an ERR if BMM (bit 2) is cleared.
Target Abort Received Event (Read/Write-1-to-Clear). This bit is asserted due to the
reception of a target abort on PCI. Write 1 to clear. TARE (MSR 50002010h[29]) must be
set to enable this event. The event causes an ERR if TARM (bit 1) is cleared.
Master Abort Received Event (Read/Write-1-to-Clear). This bit is asserted due to the
reception of a master abort on PCI. Write 1 to clear. MARE (MSR 50002010h[28]) must
be set to enable this event. The event causes an ERR if MARM (bit 0) is cleared.
Reserved (Read Only). Reserved for future use.
Parity Error Mask. Clear to allow PARE (bit 21) to generate an ERR.
System Error Mask. Clear to allow SYSE (bit 20) to generate an ERR.
Reserved (Read Only). Reserved for future use.
Broken Master Mask. Clear to allow BME (bit 18) to generate an ERR.
Target Abort Received Mask. Clear to allow TARE (bit 17) to assert ERR.
Master Abort Received Mask. Clear to allow MARE (bit 16) to assert ERR.
GLD_MSR_ERROR Bit Descriptions
GLD_MSR_ERROR Register Map
RSVD
RSVD
9
8
33234C
7
6
5
4
3
2
1
573
0