ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 61

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GLIU Register Descriptions
4.2.2.2
MSR Address
Type
Reset Value
Ports that are not implemented return 00 (RSVD). Ports that are slave only return 11. Master/Slave ports return the values
as stated.
GLIU0 will reset all PAE to 11 (ON) except that GLIU0 PAE3 resets to 00 when the debug stall bootstrap is active (CPU port
resets inactive for debug stall).
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:16
15:14
13:12
11:10
Bit
9:8
7:6
5:4
3:2
1:0
Port Active Enable (PAE)
Name
RSVD
PAE0
PAE7
PAE6
PAE5
PAE4
PAE3
PAE2
PAE1
GLIU0: 10000081h
GLIU1: 40000081h
R/W
Boot Strap Dependent
RSVD
Description
Reserved.
Port Active Enable for Port 0 (GLIU0: GLIU; GLIU1: GLIU).
00: OFF - Master transactions are disabled.
01: LOW - Master transactions limited to 1 outstanding transaction.
10: Reserved.
11: ON - Master transactions enabled with no limitations.
Port Active Enable for Port 7 (GLIU0: Not Used; GLIU1: Not Used).
See bits [15:14] for decode.
Port Active Enable for Port 6(GLIU0: Not Used; GLIU1: SB (Security Block)).
See bits [15:14] for decode.
Port Active Enable for Port 5 (GLIU0: GP; GLIU1: VIP).
See bits [15:14] for decode.
Port Active Enable for Port 4 (GLIU0: DC; GLIU1: GLPCI).
See bits [15:14] for decode.
Port Active Enable for Port 3 (GLIU0: CPU Core; GLIU1: GLCP).
See bits [15:14] for decode.
Port Active Enable for Port 2 (GLIU0: Interface to GLIU1; GLIU1: VP).
Port Active Enable for Port 1 (GLIU0: GLMC; GLIU1: Interface to GLIU0).
See bits [15:14] for decode.
See bits [15:14] for decode.
PAE Bit Descriptions
PAE Register Map
RSVD
PAE0
PAE7
PAE6
9
PAE5
8
33234C
7
PAE4
6
5
PAE3
4
3
PAE2
2
1
PAE1
0
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