ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 665
ALXD800EEXJ2VD
Manufacturer Part Number
ALXD800EEXJ2VD
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJ2VD.pdf
(675 pages)
Specifications of ALXD800EEXJ2VD
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Instruction Set
AMD Geode™ LX Processors Data Book
FEMMS Faster Exit of the MMX or
3DNow! State
PAVGUSB Average of Unsigned Packed 8-Bit Values
PF2ID Converts Packed Floating-Point Operand to Packed 32-Bit Integer
PF2IW Packed Floating-Point to Integer Word Conversion with Sign Extend
PFACC Floating-Point Accumulate
PFADD Packed Floating-Point Addition
PFCMPEQ Packed Floating-Point Comparison, Equal to
PFCMPGE Packed Floating-Point Comparison, Greater Than or Equal to
PFCMPGT Packed Floating- Point Comparison, Greater Than
MMX Register 1 with MMX Register2
MMX Register with Memory64
MMX Register 1 by MMX Register2
MMX Register 1 by Memory64
MMX Register1 by MMX Register2
MMX Register by Memory64
MMX Register 1 with MMX Register2
MMX Register 1 with Memory64
MMX Register1 with MMX Register2
MMX Register1 with Memory64
MMX Register 1with MMX Register 2
MMX Register with Memory64
MMX Register 1 with MMX Register2
MMX Register with Memory64
MMX Register1 with MMX Register2
MMX Register with Memory64
3DNow!™ Instructions
Table 8-30. 3DNow!™ Technology Instruction Set
0F0E
0F0F [11 mm1
mm2] BF
0F0F [mod mm r/m]
BF
0F0F [11 mm1
mm2] 1D
0F0F [mod mm r/m]
1D
0F0F [11 mm1
mm2] 1C
0F0F [mod mm r/m]
1C
0F0F [11 mm1
mm2] AE
0F0F [mod mm r/m]
AE
0F0F [11 mm1
mm2] 9E
0F0F [mod mm r/m]
9E
0F0F [11 mm1
mm2] B0
0F0F [mod mm r/m]
B0
0F0F [11 mm1
mm2] 90
0F0F [mod mm r/m]
90
0F0F [11 mm1
mm2] A0
0F0F [mod mm r/m]
A0
Opcode/imm8
Tag Word <--- FFFFh (empties the floating point tag word)
MMX registers <--- undefined value
[byte] + 01h)/2
MMX reg [byte] <--- rounded up --- (MMX reg 1 [byte] + Memory [byte]
+ 01h)/2
MMX reg 1 [dword] <--- Sat integer --- MMX reg 2 [dword]
MMX reg 1 [dword] <--- Sat integer --- Memory64 [dword]
MMX reg 1 [dword] <--- integer sign extended --- sat --- MMX reg 2
[dword]
MMX reg [dword] <--- integer sign extended --- sat --- Memory64
[dword]
MMX reg 1 [low dword] <--- MMX reg 1 [low dword] + MMX reg 1 [high
dword]
MMX reg 1 [high dword] <--- MMX reg 2 [low dword] + MMX reg 2 [high
dword]
MMX reg 1 [low dword] <--- MMX reg 1[low dword] + MMX reg 1 [high
dword]
MMX reg 1 [high dword] <--- Memory64 [low dword] + Memory64 [high
dword]
MMX reg 1[dword] <--- MMX reg 1 [dword] + MMX reg 2 [dword]
MMX reg 1 [dword] <--- MMX reg 1 [dword] + Memory64 [dword]
MMX reg 1 [dword] <--- FFFF FFFFh --- if (MMX reg 1 [dword] = MMX
reg 2 [dword])
MMX [dword] <--- 0000 0000 h --- if (MMX reg 1 [dword] NOT + MMX
reg 2 [dword])
MMX reg [dword] <--- FFFF FFFFh --- if (MMX reg [dword] =
Memory64 [dword])
MMX reg [dword] <---0000 0000h --- if (MMX reg [dword] NOT =
Memory64 [dword])
MMX reg 1 [dword] <--- FFFF FFFFh --- if (MMX reg 1 [dword]
reg 2 [dword])
MMX reg 1 [dword] <---0000 0000h --- if (MMX reg 1 [dword] NOT
MMX reg 2 [dword])
MMX reg 1 [dword] <--- FFFF FFFFh --- if (MMX reg 1[dword]
Memory64 [dword])
MMX reg [dword] <--- 0000 0000h --- if (MMX reg [dword] NOT
Memory64 [dword])
MMX reg 1 [dword] <--- FFFF FFFFh --- if (MMX reg 1 [dword]
reg 2 [dword])
MMX reg 1 [dword] <---0000 0000h --- if (MMX reg 1 [dword] NOT
MMX reg 2 [dword])
MMX reg [dword] <---FFFF FFFFh --- if (MMX reg [dword]
[dword])
MMX reg [dword] <--- 0000 0000h --- if (MMX reg [dword] NOT
Memory64 [dword])
MMX reg1 [byte] <--- rounded up --- (MMX reg 1 [byte] + MMX reg 2
Operation
33234C
>
Memory64
>
>
>
>
>
MMX
MMX
>
>
Cnt
Clk
1
2
2
2
2
2
2
2
2
Notes
1
665
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