ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 572

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.16.1.3 GLD SMI MSR (GLD_MSR_SMI)
MSR Address
Type
Reset Value
572
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:22
15:6
Bit
21
20
19
18
17
16
5
4
3
2
1
0
Name
RSVD (RO)
PARE
SYSE
VPHE
BME
TARE
MARE
RSVD
PARM
SYSM
VPHM
BMM
TARM
MARM
RSVD
50002002h
R/W
00000000_0000003Fh
33234C
Description
Reserved (Read Only). Reserved for future use.
Parity Error Event (Read/Write-1-to-Clear). This bit is asserted due to detection of a
PCI bus parity error. Write 1 to clear. PS (MSR 50002010h[27]) must be set to enable this
event. The event causes an ASMI if PARM (bit 5) is cleared.
System Error Event (Read/Write-1-to-Clear). This bit is asserted due to the detection
of a PCI bus system error. Write 1 to clear. PS (MSR 50002010h[27]) must be set to
enable this event. The event causes an ASMI if SYSM (bit 4) is cleared.
Virtual PCI Header Event (Read/Write-1-to-Clear). This bit is set by Virtual PCI Header
support logic, write 1 to clear. The event causes an SSMI if VPHM (bit 3) is cleared.
Broken Master Event (Read/Write-1-to-Clear). This bit is asserted due to detection of a
broken PCI bus master. Write 1 to clear. BMS (MSR 50002010h[26]) must be set to
enable this event. The event causes an ASMI if BMM (bit 2) is cleared.
Target Abort Received Event (Read/Write-1-to-Clear). This bit is asserted due to
reception of target abort on PCI. Write 1 to clear. TARS (MSR50002010h[25]) must be
set to enable this event. The event causes an ASMI if TARM (bit 1) is cleared.
Master Abort Received Event (Read/Write-1-to-Clear). This bit is asserted due to
reception of master abort on PCI. Write 1 to clear. MARS (MSR 50002010h[24]) must be
set to enable this event. The event causes an ASMI if MARM (bit 0) is cleared.
Reserved. Reserved for future use.
Parity Error Mask. Clear to allow PARE (bit 21) to generate an ASMI.
System Error Mask. Clear to allow SYSE (bit 20) to generate an ASMI.
Virtual PCI Header Mask. Clear to allow SSMI flag to be set in selected GLIU response
packets. I/O reads and writes to location 0CFCh may cause an SSMI depending upon
the configuration of this bit and the GLPCI_PBUS (MSR 50002012h) model specific reg-
isters.
Broken Master Mask. Clear to allow BME (bit 18) to generate an ASMI.
Target Abort Received Mask. Clear to allow TARE (bit 17) to generate an ASMI.
Master Abort Received Mask. Clear to allow MARE (bit 16) to generate an ASMI.
GLD_MSR_SMI Bit Descriptions
GLD_MSR_SMI Register Map
RSVD
RSVD
GeodeLink™ PCI Bridge Register Descriptions
AMD Geode™ LX Processors Data Book
9
8
7
6
5
4
3
2
1
0