ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 539

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Control Processor Register Descriptions
6.14.1.4 GLD Error MSR (GLD_MSR_ERROR)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:36
31:4
Bit
35
34
33
32
3
2
1
0
Name
RSVD
ERR_SYSPLL
ERR_DOTPLL
ERR_SIZE
ERR_TYPE
RSVD
ERR_SYSPLL_MASK
ERR_DOTPLL_MASK
ERR_SIZE_MASK
ERR_TYPE_MASK
4C002003h
R/W
00000000_00000000h
Description
Reserved.
Error System PLL. System PLL lock signal was active when POR was inactive.
Writing 1 clears error; 0 leaves unchanged.
Error Dot Clock PLL. Dot clock PLL lock signal was active when POR was inac-
tive. Writing 1 clears error; 0 leaves unchanged.
Error Size. The GLIU interface detected a read or write of more than 1 data
packet (size = 16 bytes or 32 bytes). If a response packet is expected, the excep-
tion bit will be set, in all cases the asynchronous error signal will be set. Writing 1
clears error; 0 leaves unchanged.
Error Type. An unexpected type was sent to the GLCP GLIU interface (start
request with BEX type, snoop, peek_write, debug_req, or NULL type). If a
response packet is expected, the exception bit will be set, in all cases the asyn-
chronous error signal will be set. Writing a 1 clears the error, writing a 0 leaves
unchanged.
Reserved.
Error System PLL Mask. When set to 1, disables error signaling based on the
state of the ERR_SYSPLL flag (bit 35).
Error Dot Clock PLL Mask. When set to 1, disables error signaling based on the
state of the ERR_DOTPLL flag (bit 34).
Error Size Mask. When set to 1, disables error signaling based on the state of
the ERR_SIZE flag (bit 33).
Error Type Mask. Wh.en set to 1, disables error signaling based on the state of
the ERR_TYPE flag (bit 32).
GLD_MSR_ERROR Bit Descriptions
GLD_MSR_ERROR Register Map
RSVD
RSVD
9
8
33234C
7
6
5
4
3
2
1
539
0