UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 135

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.2.13 Port 14
using port mode register 14 (PM14). When the P140 to P145 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14).
using port input mode register 14 (PIM14).
port output mode register 14 (POM14).
I/O, and clock I/O.
Port 14 is a 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units
Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
Output from the P142 to P144 pins can be specified as N-ch open-drain output (V
This port can also be used for timer I/O, external interrupt request input, clock/buzzer output, serial interface data
Reset signal generation sets port 14 to input mode.
Figures 4-33 to 4-35 show block diagrams of port 14.
Cautions 1. To use P142/SCK20/SCL20, P143/SI20/RxD2/SDA20, P144/SO20/TxD2 as a general-purpose
2. To use P145/TI07/TO07 as a general-purpose port, set bit 7 (TO07) of timer output register 0
3. To use P140/PCLBUZ0/INTP6 or P141/PCLBUZ1/INTP7 as a general-purpose port, set bit 7 of
port, note the serial array unit setting. For details, refer to the following tables.
(TO0) and bit 7 (TOE07) of timer output enable register 0 (TOE0) to “0”, which is the same as
their default status setting.
clock output select register 0 and 1 (CKS0, CKS1) to “0”, which is the same as their default
status setting.
• Table 12-9 Relationship Between Register Settings and Pins (Channel 0 of Unit 1: CSI20,
• Table 12-10 Relationship Between Register Settings and Pins (Channel 1 of Unit 1: UART2
UART2 Transmission, IIC20)
Reception)
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17893EJ8V0UD
DD
tolerance) in 1-bit units using
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