UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 855

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Subsystem
clock
control
CPU clock
status
transition
Timer
array unit
Function
Subsystem clock
TCR0n:
Timer/counter
register 0n
TDR0n: Timer
data register 0n
PER0:
Peripheral
enable register 0
TPS0: Timer
clock select
register 0
TMR0n: Timer
mode register 0n
TS0: Timer
channel start
register 0
TT0: Timer
channel stop
register 0
TIS0: Timer
input Select
Register 0
TOE0: Timer
output enable
register 0
TO0: Timer
output register 0
Details of
Function
−
The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the
same time.
procedure when oscillating the X1 clock or 5.6.1 (2) Example of setting procedure
when using the external main system clock.
Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the
peripheral hardware if it is operating on the subsystem clock.
The subsystem clock oscillation cannot be stopped using the STOP instruction.
Set the clock after the supply voltage has reached the operable voltage of the clock
to be set (see CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS)).
The count value is not captured to TDR0n even when TCR0n is read.
TDR0n does not perform a capture operation even if a capture trigger is input, when
it is set to the compare function.
When setting the timer array unit, be sure to set TAU0EN to 1 first. If TAU0EN = 0,
writing to a control register of the timer array unit is ignored, and all read values are
default values (except for timer input select register 0 (TIS0), input switch control
register (ISC), noise filter enable register 1 (NFEN1), port mode registers 0, 1, 3, 4,
14 (PM0, PM1, PM3, PM4, PM14), and port registers 0, 1, 3, 4, 14 (P0, P1, P3, P4,
P14)).
Be sure to clear bit 1 of the PER0 register to 0.
Be sure to clear bits 15 to 8 to “0”.
Be sure to clear bits 14, 13, 5, and 4 to “0”.
Be sure to clear bits 15 to 8 to “0”.
In the first cycle operation of count clock after writing TS0n, an error at a maximum of
one clock is generated since count start delays until count clock has been generated.
When the information on count start timing is necessary, an interrupt can be
generated at count start by setting MD0n0 = 1.
An input signal sampling error is generated since operation starts upon start trigger
detection (The error is one count clock when TI0n is used).
Be sure to clear bits 15 to 8 to “0”.
When the LIN-bus communication function is used, select the input signal of the
RxD3 pin by setting ISC1 (bit 1 of the input switch control register (ISC)) to 1 and
setting TIS07 to 0.
Be sure to clear bits 15 to 8 to “0”.
Be sure to clear bits 15 to 8 to “0”.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
For EXCLK and OSCSEL bits, see 5.6.1 (1) Example of setting
Cautions
186, 188
pp.185,
p.181
p.182
p.182
p.197
p.199
p.201
p.201
p.202
p.203
p.208
pp.209,
210
pp.211,
212
p.213
p.213
p.214
p.215
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