UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 899

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5th edition
Edition
Change of Figure 12-42. Timing Chart of Master Transmission/Reception (in
Single-Transmission/Reception Mode)
Change of Figure 12-44. Timing Chart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Figure 12-45. Flowchart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Figure 12-49. Procedure for Resuming Slave Transmission
Change of Figure 12-50. Timing Chart of Slave Transmission (in Single-
Transmission Mode)
Change of Figure 12-57. Procedure for Resuming Slave Reception
Change of Figure 12-58. Timing Chart of Slave Reception (in Single-Reception
Mode)
Change of Figure 12-63. Procedure for Resuming Slave
Transmission/Reception
Change of Figure 12-64. Timing Chart of Slave Transmission/Reception (in
Single-Transmission/Reception Mode)
Change of Figure 12-66. Timing Chart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Figure 12-67. Flowchart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Transfer data length in 12.6.2 UART reception
Change of Figure 12-80. Timing Chart of UART Reception
Change of Transfer data length in 12.6.3 LIN transmission
Change of Transfer data length in 12.6.4 LIN reception
Change of Figure 12-89. Initial Setting Procedure for Address Field
Transmission
Change of Figure 12-90. Timing Chart of Address Field Transmission
Change of Figure 12-91. Flowchart of Address Field Transmission
Change of Figure 12-92. Example of Contents of Registers for Data
Transmission of Simplified I
Change of Figure 12-94. Flowchart of Data Transmission
Change of Figure 12-95. Example of Contents of Registers for Data Reception
of Simplified I
Change of Figure 12-96. Timing Chart of Data Reception
Change of Figure 12-97. Flowchart of Data Reception and addition of Caution
Change of Figure 12-99. Flowchart of Stop Condition Generation
Addition of 12.9 Relationship Between Register Settings and Pins
Change of Table 16-1. Interrupt Source List
Addition of Note to Figure 18-3. HALT Mode Release by Interrupt Request
Generation
Addition of Note to Figure 18-5. Operation Timing When STOP Mode Is Released
(When Unmasked Interrupt Request Is Generated)
Addition of Note to Figure 18-6. STOP Mode Release by Interrupt Request
Generation
2
C (IIC10, IIC20) and addition of Note
APPENDIX C REVISION HISTORY
2
C (IIC10, IIC20) and addition of Note
User’s Manual U17893EJ8V0UD
Description
CHAPTER 12 SERIAL
ARRAY UNIT
CHAPTER 16
INTERRUPT
FUNCTIONS
CHAPTER 18
STANDBY FUNCTION
Chapter
(13/20)
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