UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 79

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

F0017H
F0030H
F0031H
F0033H
F0034H
F0035H
F0037H
F0039H
F003CH
F003EH
F0040H
F0044H
F004EH
F0050H
F0054H
F005EH
F0060H
F0061H
F00F0H
F00F2H
F00F3H
F00F4H
F00FEH
F0100H
F0101H
F0102H
F0103H
F0104H
F0105H
F0106H
F0107H
F0108H
F0109H
F010AH
F010BH
F010CH
F010DH
F010EH
F010FH
Address
A/D port configuration register
Pull-up resistor option register 0
Pull-up resistor option register 1
Pull-up resistor option register 3
Pull-up resistor option register 4
Pull-up resistor option register 5
Pull-up resistor option register 7
Pull-up resistor option register 9
Pull-up resistor option register 12
Pull-up resistor option register 14
Port input mode register 0
Port input mode register 4
Port input mode register 14
Port output mode register 0
Port output mode register 4
Port output mode register 14
Noise filter enable register 0
Noise filter enable register 1
Peripheral enable register 0
Internal high-speed oscillator trimming register
Operation speed mode control register
Regulator mode control register
BCD adjust result register
Serial status register 00
Serial status register 01
Serial status register 02
Serial status register 03
Serial flag clear trigger register 00
Serial flag clear trigger register 01
Serial flag clear trigger register 02
Serial flag clear trigger register 03
Special Function Register (SFR) Name
Table 3-6. Extended SFR (2nd SFR) List (1/5)
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17893EJ8V0UD
ADPC
PU0
PU1
PU3
PU4
PU5
PU7
PU9
PU12
PU14
PIM0
PIM4
PIM14
POM0
POM4
POM14
NFEN0
NFEN1
PER0
HIOTRM
OSMC
RMC
BCDADJ
SSR00L
SSR01L
SSR02L
SSR03L
SIR00L
SIR01L
SIR02L
SIR03L
−
−
−
−
−
−
−
−
Symbol
SSR00
SSR01
SSR02
SSR03
SIR00
SIR01
SIR02
SIR03
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
Manipulable Bit Range
1-bit
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
8-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
−
√
−
√
−
√
−
√
−
16-bit
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
After Reset
Undefined
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
10H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
10H
00H
00H
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