UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 441

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UPD78F1152AGC-GAD-AX

Manufacturer Part Number
UPD78F1152AGC-GAD-AX
Description
MCU 16BIT 78K0R/KX3 80-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1152AGC-GAD-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
65
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number:
UPD78F1152AGC-GAD-AX
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Renesas Electronics America
Quantity:
10 000
12.6.1 UART transmission
stop synchronization).
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
Remarks 1. f
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
UART transmission is an operation to transmit data from the 78K0R/KF3 to another device asynchronously (start-
Of two channels used for UART, the even channel is used for UART transmission.
specifications (see CHAPTER 28
CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
UART
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
f
MCK
CLK
: System clock frequency
: Operation clock (MCK) frequency of target channel
Channel 0 of SAU0
TxD0
INTST0
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
None
5, 7, or 8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
MCK
UART0
/6 [bps] (SDRmn [15:9] = 2 or more), Min. f
CHAPTER 12 SERIAL ARRAY UNIT
User’s Manual U17893EJ8V0UD
ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
Channel 2 of SAU0
TxD1
INTST1
UART1
CLK
TxD2
INTST2
Channel 0 of SAU1
/(2 × 2
11
UART2
× 128) [bps]
Note
Channel 2 of SAU1
TxD3
INTST3
UART3
439

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