UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 493

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note1
SE
10
0
1
0
1
0
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
Remark X: Don’t care
102
MD
0
0
1
0
0
1
101
MD
0
1
0
0
1
0
2. When channel 1 of unit 1 is set to UART2 reception, this pin becomes an RxD2 function pin (refer to Table
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output
5. When using UART2 transmission and reception in a pair, set channel 1 of unit 1 to UART2 reception (refer
6. Set the CKO10 bit to 1 before a start condition is generated. Clear the SO10 bit from 1 to 0 when the start
7. Set the CKO10 bit to 1 before a stop condition is generated. Clear the SO10 bit from 0 to 1 when the stop
SOE
12-10). In this case, operation stop mode or UART2 transmission must be selected for channel 0 of unit 1.
register m (SOm).
to Table 12-10).
condition is generated.
condition is generated.
10
0
0
1
1
0
1
1
1
0
1
1
1
0
Note4
Note4
Note4
Note4
Note4
Note6
Note4
Note4
Note4
Note7
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
SO
10
1
1
1
CKO
Note4
Note4
Note4
Note6
Note4
Note4
Note4
Note7
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
10
1
1
1
1
1
TXE
10
0
0
1
1
0
1
1
1
0
1
0
1
1
0
0
1
0
Table 12-9. Relationship between register settings and pins
(Channel 0 of unit 1: CSI20, UART2 transmission, IIC20)
RXE
10
0
1
0
1
1
0
1
0
0
0
1
0
0
1
0
0
1
Note3
Note3
142
PM
×
1
1
1
0
0
0
×
0
0
0
0
0
P142 PM
Note3
Note3
CHAPTER 12 SERIAL ARRAY UNIT
×
×
×
×
1
1
1
×
1
1
1
1
1
Note3
Note3
Note3
Note3
Note2
143
User’s Manual U17893EJ8V0UD
×
1
×
1
1
×
1
×
0
0
0
0
0
P143
Note3
Note3
Note3
Note3
Note2
×
×
×
×
×
×
×
×
1
1
1
1
1
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
144
PM
×
×
0
0
×
0
0
0
×
×
×
×
×
P144
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
×
×
1
1
×
1
1
1
×
×
×
×
×
transmission/reception
transmission/reception
IIC20 address field
Operation mode
transmission
Operation stop
start condition
Master CSI20
Master CSI20
stop condition
Slave CSI20
Slave CSI20
transmission
transmission
transmission
Master CSI20
transmission
Slave CSI20
IIC20 data
IIC20 data
reception
reception
reception
UART2
mode
IIC20
IIC20
Note5
SCL20/P142
SCK20/
(output)
(output)
(output)
SCK20
SCK20
SCK20
SCK20
SCK20
SCK20
SCL20
SCL20
SCL20
SCL20
SCL20
(input)
(input)
(input)
P142
P142
Pin Function
SI20/SDA20/
RxD2/P143
P143/RxD2
P143/RxD2
SDA20
SDA20
SDA20
SDA20
SDA20
P143
P143
P143
P143
SI20
SI20
SI20
SI20
Note2
TxD2/P144
491
SO20/
SO20
SO20
SO20
SO20
TxD2
P144
P144
P144
P144
P144
P144
P144
P144