UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 875

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Low-
voltage
detector
Regulator
Option
byte
Function
Cautions for low-
voltage detector
RMC: Regulator
mode control
register
000C0H/010C0H Set the same value as 000C0H to 010C0H when the boot swap operation is used
000C1H/010C1H Set the same value as 000C1H to 010C1H when the boot swap operation is used
000C2H/010C2H Set FFH to 010C2H when the boot swap operation is used because 000C2H is
000C3H/010C3H Set the same value as 000C3H to 010C3H when the boot swap operation is used
000C0H/010C0H The watchdog timer continues its operation during self-programming of the flash
Setting of option
byte
000C1H/010C1H
000C3H/010C3H Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value.
Details of
Function
−
There is some delay from the time supply voltage (V
until the time LVI reset has been generated.
In the same way, there is also some delay from the time LVI detection voltage (V
≤ supply voltage (V
See the timing in Figure 20-2 (2) When LVI is ON upon power application (option
byte: LVIOFF = 0) for the reset processing time until the normal operation is entered
after the LVI reset is released.
The RMC register can be rewritten only in the low consumption current mode (refer
to Table 22-1). In other words, rewrite this register during CPU operation with the
subsystem clock (f
speed oscillation clock (f
When using the setting fixed to the low consumption current mode, the RMC register
can be used in the following cases.
<When X1 clock is selected as the CPU clock>
f
<When the internal high-speed oscillation clock, external input clock, or subsystem
clock are selected for the CPU clock>
f
The self-programming function is disabled in the low consumption current mode.
Be sure to set FFH to 000C2H (000C2H/010C2H when the boot swap operation is
used).
because 000C0H is replaced by 010C0H.
because 000C1H is replaced by 010C1H.
replaced by 010C2H.
because 000C3H is replaced by 010C3H.
memory and EEPROM emulation. During processing, the interrupt acknowledge
time is delayed.
consideration.
Be sure to set bits 7 to 1 to “1”.
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
Be sure to set 000010B to bits 6 to 1.
To specify the option byte by using assembly language, use OPT_BYTE as the
relocation attribute name of the CSEG pseudo instruction. To specify the option byte
to 010C0H to 010C3H in order to use the boot swap function, use the relocation
attribute AT to specify an absolute address.
X
CLK
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
≤ 5 MHz and f
≤ 5 MHz
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
CLK
DD
Set the overflow time and window size taking this delay into
XT
≤ 5 MHz
) until the time LVI reset has been released (see Figure 21-12).
) while the high-speed system clock (f
IH
) are both stopped.
Cautions
DD
) < LVI detection voltage (V
MX
) and internal high-
LVI
LVI
μ
s
)
)
p.674
p.674
p.674
p.676
p.676
p.676
p.676
p.677
p.678
p.673
p.678
p.678
p.679
p.680
(28/34)
873
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