UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 872

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

870
Reset
function
Power-on-
clear
circuit
Low-
voltage
detector
Function
Block diagram of
reset function
Watchdog timer
overflow
RESF: Reset
control flag
register
Timing of
generation of
internal reset
signal (LVIOFF =
1)
Timing of
generation of
internal reset
signal (LVIOFF =
0)
Cautions for
power-on-clear
circuit
LVIM: Low-
voltage detection
register
LVIS: Low-
voltage detection
level select
register
Details of
Function
−
Input voltage from external input pin (EXLVI) must be EXLVI < V
An LVI circuit internal reset does not reset the LVI circuit.
A watchdog timer internal reset resets the watchdog timer.
Do not read data by a 1-bit memory manipulation instruction.
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF
flag may become 1 from the beginning depending on the power-on waveform.
If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset
signal is not released until the supply voltage (V
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
Set the low-voltage detector by software after the reset status is released (see
CHAPTER 21 LOW-VOLTAGE DETECTOR).
Set the low-voltage detector by software after the reset status is released (see
CHAPTER 21 LOW-VOLTAGE DETECTOR).
In a system where the supply voltage (V
vicinity of the POC detection voltage (V
released from the reset status. In this case, the time from release of reset to the start
of the operation of the microcontroller can be arbitrarily set by taking the following
action.
To stop LVI, follow either of the procedures below.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
When LVI is used in interrupt mode (LVIMD = 0) and LVISEL is set to 0, an interrupt
request signal (INTLVI) that disables LVI operation (clears LVION) when the supply
voltage (V
voltage of external input pin (EXLVI) is less than or equal to the detection voltage
(V
Be sure to clear bits 4 to 7 to “0”.
EXLVI
)) is generated and LVIIF may be set to 1.
APPENDIX B LIST OF CAUTIONS
DD
User’s Manual U17893EJ8V0UD
) is less than or equal to the detection voltage (V
Cautions
POC
), the system may be repeatedly reset and
DD
) fluctuates for a certain period in the
DD
) exceeds 2.07 V ±0.2 V.
LVI
) (if LVISEL = 1, input
DD
.
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