UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 870

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

868
Interrupt
functions
Key
interrupt
function
Standby
function
Function
EGP0, EGP1:
External
interrupt rising
edge enable
registers, EGN0,
EGN1: External
interrupt falling
edge enable
registers
Software
interrupt request
acknowledgment
BRK instruction
KRM: Key return
mode register
OSTC:
Oscillation
stabilization time
counter status
register
Details of
Function
−
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal high-
speed oscillation clock is being used as the CPU clock, set the oscillation stabilization
time as follows.
Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
Do not use the RETI instruction for restoring from the software interrupt.
The BRK instruction is not one of the above-listed interrupt request hold instructions.
However, the software interrupt activated by executing the BRK instruction causes
the IE flag to be cleared.
generated during execution of the BRK instruction, the interrupt request is not
acknowledged.
If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of
the corresponding pull-up resistor register 7 (PU7) to 1.
An interrupt will be generated if the target bit of the KRM register is set while a low
level is being input to the key interrupt input pin. To ignore this interrupt, set the
KRM register after disabling interrupt servicing by using the interrupt mask flag.
Afterward, clear the interrupt request flag and enable interrupt servicing after waiting
for the key interrupt input low-level width (250 ns or more).
The bits not used in the key interrupt mode can be used as normal ports.
The STOP mode can be used only when the CPU is operating on the main system
clock. The STOP mode cannot be set while the CPU operates with the subsystem
clock. The HALT mode can be used when the CPU is operating on either the main
system clock or the subsystem clock.
When shifting to the STOP mode, be sure to stop the peripheral hardware operation
operating with main system clock before executing STOP instruction.
The following sequence is recommended for operating current reduction of the A/D
converter when the standby function is used: First clear bit 7 (ADCS) and bit 0
(ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion
operation, and then execute the STOP instruction.
It can be selected by the option byte whether the internal low-speed oscillator
continues oscillating or stops in the HALT or STOP mode.
CHAPTER 23 OPTION BYTE.
After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
OSTS
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
Therefore, even if a maskable interrupt request is
Cautions
For details, see
p.610
p.614
p.618
p.620
p.620
p.620
p.621
p.621
p.621
p.621
p.622
p.622
p.622
(23/34)
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