UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 274

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

272
Operation
start
During
operation
Operation
stop
TAU stop
Remarks 1.
Sets TOE0p and TOE0q (slave) to 1 (only when
operation is resumed).
The TS0n bit (master), and TS0p and TS0q (slave) bits of
the TS0 register are set to 1 at the same time.
Set values of the TMR0n, TMR0p, TMR0q registers,
TOM0n, TOM0p, TOM0q, TOL0n, TOL0p, and TOL0q
bits cannot be changed.
Set values of the TDR0n, TDR0p, and TDR0q registers
can be changed after INTTM0n of the master channel is
generated.
The TCR0n, TCR0p, and TCR0q registers can always be
read.
The TSR0n, TSR0p, and TSR0q registers are not used.
Set values of the TO0 and TOE0 registers can be
changed.
TOE0p or TOE0q of slave channel is cleared to 0
and value is set to the TO0p and TO0q bits.
To hold the TO0p and TO0q pin output levels
When holding the TO0p and TO0q pin output levels is not
necessary
The TAU0EN bit of the PER0 register is cleared to 0.
The TT0n bit (master), TT0p, and TT0q (slave) bits are
set to 1 at the same time.
The TT0n, TT0p, and TT0q bits automatically return to
0 because they are trigger bits.
Figure 6-69. Operation Procedure When Multiple PWM Output Function Is Used (2/2)
The TS0n, TS0p, and TS0q bits automatically return to
0 because they are trigger bits.
Clears TO0p and TO0q bits to 0 after
the value to be held is set to the port register.
Switches the port mode register to input mode.
2. p = n + 1; q = n + 2
n = 0, 2, 4
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17893EJ8V0UD
TE0n = 1, TE0p, TE0q = 1
The counter of the master channel loads the TDR0n value
to TCR0n and counts down. When the count value
reaches TCRn = 0000H, INTTM0n output is generated. At
the same time, the value of the TDR0n register is loaded to
TCR0n, and the counter starts counting down again.
At the slave channel 1, the values of TDR0p are transferred
to TCR0p, triggered by INTTM0n of the master channel,
and the counter starts counting down. The output levels of
TO0p become active one count clock after generation of
the INTTM0n output from the master channel. It becomes
inactive when TCR0p = 0000H, and the counting operation
is stopped.
At the slave channel 2, the values of TDR0q are transferred
to TDR0q, triggered by INTTM0n of the master channel,
and the counter starts counting down. The output levels of
TO0q become active one count clock after generation of
the INTTM0n output from the master channel. It becomes
inactive when TCR0q = 0000H, and the counting operation
is stopped.
After that, the above operation is repeated.
TE0n, TE0p, TE0q = 0, and count operation stops.
The TO0p and TO0q pins output the TO0p and TO0q set
levels.
The TO0p and TO0q pin output levels are held by port
function.
The TO0p and TO0q pin output levels go into Hi-Z output
state.
Power-off status
current status.
TCR0n, TCR0p, and TCR0q hold count value and stops.
The TO0p and TO0q output is not initialized but holds
When the master channel starts counting, INTTM0n is
generated. Triggered by this interrupt, the slave
channel also starts counting.
All circuits are initialized and SFR of each channel is
also initialized.
(The TO0p and TO0q bits are cleared to 0 and the
TO0p and TO0q pins are set to port mode.)
Hardware Status