UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 888

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

886
2nd edition
Edition
Addition of Cautions 1 and 2 to 4.2.1 Port 0
Addition of Cautions 1 and 2 to 4.2.2 Port 1
Addition of Caution to 4.2.4 Port 3
Addition of Cautions 2 and 3 to 4.2.5 Port 4
Modification of Figure 4-28 Block Diagram of P80 to P87 and Figure 4-29 Block
Diagram of P110 and P111
Addition of Caution to 4.2.12 Port 13
Addition of Cautions 1 and 2 to 4.2.13 Port 14
Addition of Caution to Figure 4-39 Format of Port Mode Register
Modification of Note in 4.3 (2) Port registers (P0 to P8, P11 to P15)
Addition of 4.4.4 Connecting to external device with different power supply
voltage (3 V)
Addition of Note to Figure 5-3 Format of Memory Extension Mode Control
Register (MEM)
Modification of description in 5.6 (5) ASTB pin and (6) EX0 to EX7, EX8 to EX15,
EX16 to EX23, and EX24 to EX31 pins
Modification of Figure 5-9 Example of Synchronous Memory Connection and
Figure 5-10 Example of Asynchronous Memory Connection
Addition of Cautions 3 to Figure 6-3 Format of Clock Operation Status Control
Register (CSC)
Modification of description in 6.3 (3) Oscillation stabilization time counter status
register (OSTC)
Modification of Cautions 2 in Figure 6-4 Format of Oscillation Stabilization Time
Counter Status Register (OSTC)
Modification of Cautions 5 in Figure 6-5 Format of Oscillation Stabilization Time
Select Register (OSTS)
Modification of Cautions 3 in Figure 6-6 Format of System Clock Control
Register (CKC)
Modification of Cautions 1 to 3 in Figure 6-8 Format of Operation Speed Mode
Control Register (OSMC)
Addition of Figure 6-14 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1)) and description
Addition of Figure 6-15 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Enabled Is Set (Option Byte:
LVIOFF = 0)) and description
Modification of Cautions 1 in 6.6.1 (1) Example of setting procedure when
oscillating the X1 clock
Modification of register name in title of 6.6.1 (2) <2>
Addition of <2> to 6.6.1 (4) (b)
Addition of Caution to 6.6.2 (2) (b)
Modification of Caution in 6.6.3 Example of controlling subsystem clock
Modification of Caution in 6.6.3 (1) Example of setting procedure when oscillating
the subsystem clock
Modification of bit name in 6.6.3 (2) <2> Setting the subsystem clock as the
source clock of the CPU clock (CKC register)
Modification of Caution in 6.6.3 (2) Example of setting procedure when using the
subsystem clock as the CPU clock
Modification of register name in title of 6.6.3 (3) <2>
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
Description
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5
EXTERNAL BUS
INTERFACE
CHAPTER 6 CLOCK
GENERATOR
Chapter
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