UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 898

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

896
5th edition
Edition
Change of Cautions 1 and Cautions 2 in 8.3 (1) Watchdog timer enable register
(WDTE)
Change of address in Figure 3-16. Configuration of General-Purpose Registers
Addition of register and Note in Table 3-5. SFR List
Addition of PIM register and POM register in block diagram
Change of corresponding pins of EV
Supplies
Change of Cautions 1 and Cautions 2 in 4.2.1 Port 0
Change of Cautions 1, Cautions 2, and Cautions 3 in 4.2.2 Port 1
Change of Cautions 1 and addition of Cautions 2 in 4.2.4 Port 3
Change of Cautions 2 and Cautions 3 in 4.2.5 Port 4
Addition of Caution to 4.2.7 Port 6
Change of Cautions 1 and Cautions 2 and addition of Cautions 3 to 4.2.13 Port
14
Addition description to (4) Port input mode registers (PIM0, PIM4, PIM14) and (5)
Port output mode registers (POM0, POM4, POM14) in 4.3
Addition of Notes 3 to Figure 5-6 Format of System Clock Control Register
(CKC)
Addition of Cautions 5 to Figure 5-8. Format of Operation Speed Mode Control
Register (OSMC)
Change of Table 6-1. Configuration of Timer Array Unit
Change of description of MASTER0n bit in Figure 6-6. Format of Timer Mode
Register 0n (TMR0n) (1/3)
Addition of Caution to Figure 6-16. Format of Timer Input Select Register 0
(TIS0)
Addition of description to 6.3 (10) Timer output register 0 (TO0)
Addition of description and change of Remark in 6.3 (12) Timer output mode
register 0 (TOM0)
Change of Remark in Figure 6-21. Format of Input Switch Control Register (ISC)
Change of Cautions 1 in Figure 7-2. Format of Peripheral Enable Register 0
(PER0)
Addition of description to 7.3 (15) Alarm hour register (ALARMWH)
Addition of Note to Figure 7-18. Procedure for Starting Operation of Real-Time
Counter
Change of Figure 12-1. Block Diagram of Serial Array Unit 0
Change of Figure 12-2. Block Diagram of Serial Array Unit 1
Addition of Note to Figure 12-7. Format of Serial Communication Operation
Setting Register mn (SCRmn) (2/3)
Change of description in 12.3 (12) Serial output register m (SOm)
Addition of 12.4 Operation stop mode
Change of description in (a) Serial output register m (SOm)
Change of Figure 12-27. Procedure for Resuming Master Transmission
Change of Figure 12-36. Timing Chart of Master Reception (in Single-Reception
Mode)
Change of Figure 12-41. Procedure for Resuming Master
Transmission/Reception
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
DD
Description
and V
DD
in Table 4-1. Pin I/O Buffer Power
CHAPTER 8
WATCHDOG TIMER
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 TIMER
ARRAY UNIT
CHAPTER 7 REAL-
TIME COUNTER
CHAPTER 12 SERIAL
ARRAY UNIT
Chapter
(12/20)