UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 867

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Serial
interface
IIC0
Function
IICF0: IIC flag
register 0
IICX0: IIC
function
expansion
register 0
Setting transfer
clock
When STCEN =
0
When STCEN =
1
If other I
communications
are already in
progress
Setting transfer
clock frequency
STT0, SPT0:
Bits 1, 0 of IIC
control register 0
(IICC0)
Details of
Function
2
C
As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
status when STCEN = 1, when generating the first start condition (STT0 = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
Write to IICRSV only when the operation is stopped (IICE0 = 0).
Determine the transfer clock frequency of I
CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0
(IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0.
Determine the transfer clock frequency of I
CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0
(IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0.
Immediately after I
(IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status. When
changing from a mode in which no stop condition has been detected to a master
device communication mode, first generate a stop condition to release the bus, then
perform master device communication.
When using multiple masters, it is not possible to perform master device
communication when the bus has not been released (when a stop condition has not
been detected).
Use the following sequence for generating a stop condition.
<1> Set IIC clock select register 0 (IICCL0).
<2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
<3> Set bit 0 (SPT0) of IICC0 to 1.
Immediately after I
(IICBSY = 0) is recognized regardless of the actual bus status. To generate the first
start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is necessary to
confirm that the bus has been released, so as to not disturb other communications.
If I
progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I
recognizes that the SDA0 pin has gone low (detects a start condition). If the value on
the bus at this time can be recognized as an extension code, ACK is returned, but
this interferes with other I
sequence.
<1> Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request
<2> Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after
Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0
of IICL0), and CLX0 (bit 0 of IICX0) before enabling the operation (IICE0 = 1). To
change the transfer clock frequency, clear IICE0 to 0 once.
Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before
they are cleared to 0 is prohibited.
2
C operation is enabled and the device participates in communication already in
signal (INTIIC0) when the stop condition is detected.
setting IICE0 to 1), to forcibly disable detection.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
2
C operation is enabled (IICE0 = 1), the bus communication status
2
C operation is enabled (IICE0 = 1), the bus released status
2
C communications. To avoid this, start I
Cautions
2
2
C by using CLX0, SMC0, CL01, and
C by using CLX0, SMC0, CL01, and
2
C.
2
C in the following
2
C
p.508
p.508
p.510
p.516
p.530
p.530
p.530
p.530
p.530
(20/34)
865
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