UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 575

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) DMA byte count register n (DBCn)
Address: FFFB6H, FFFB7H (DBC0), FFFB8H, FFFB9H (DBC1)
(n = 0, 1)
DBCn
This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to
set the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times).
Each time DMA transfer has been executed, this register is automatically decremented. By reading this
DBCn register during DMA transfer, the remaining number of times of transfer can be learned.
DBCn can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 0000H.
Cautions 1. Be sure to clear bits 15 to 10 to “0”.
Remark
DBCn[9:0] Number of Times of Transfer
15
0
3FEH
3FFH
000H
001H
002H
003H
2. If the general-purpose register is specified or the internal RAM space is exceeded as a
n: DMA channel number (n = 0, 1)
•
•
•
result of continuous transfer, the general-purpose register or SFR space are written or
read, resulting in loss of data in these spaces. Be sure to set the number of times of
transfer that is within the internal RAM space.
14
0
Figure 15-3. Format of DMA Byte Count Register n (DBCn)
13
(When DBCn is Written)
0
DBC0H: FFFB7H
DBC1H: FFFB9H
12
0
1024
1022
1023
1
2
3
•
•
•
11
CHAPTER 15 DMA CONTROLLER
0
User’s Manual U17893EJ8V0UD
10
0
9
Completion of transfer or waiting for 1024 times of DMA transfer
8
Waiting for remaining three times of DMA transfer
Waiting for remaining 1022 times of DMA transfer
Waiting for remaining 1023 times of DMA transfer
Waiting for remaining two times of DMA transfer
Waiting for remaining one time of DMA transfer
After reset: 0000H
Remaining Number of Times of Transfer
7
6
(When DBCn is Read)
5
DBC0L: FFFB6H
DBC1L: FFFB8H
•
•
•
R/W
4
3
2
1
0
573