UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 484

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UPD78F1152AGC-GAD-AX

Manufacturer Part Number
UPD78F1152AGC-GAD-AX
Description
MCU 16BIT 78K0R/KX3 80-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1152AGC-GAD-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
65
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1152AGC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.7.4 Stop condition generation
released.
482
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is
(1) Processing flow
SDAr output
SCLr output
Note During the receive operation, the SOEmn bit is set to 0 before receiving the last data.
Remark
SOEmn
SEmn
STmn
Note
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
Figure 12-103. Timing Chart of Stop Condition Generation
Figure 12-104. Flowchart of Stop Condition Generation
Operation
stop
CHAPTER 12 SERIAL ARRAY UNIT
Writing 1 to STmn bit to clear
Starting generation of stop condition.
transmission/data reception
End of IIC communication
Writing 0 to SOEmn bit
Writing 1 to CKOmn bit
(SEmn is cleared to 0)
Writing 0 to SOmn bit
Writing 1 to SOmn bit
User’s Manual U17893EJ8V0UD
SOmn bit
manipulation
Completion of data
Wait
Stop condition
CKOmn bit
manipulation
SOmn bit
manipulation
Secure a wait time so that the specifications of
I
2
C on the slave side are satisfied.

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