UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 586

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

using software in this example.
be received when the first buffer empty interrupt occurs is invalid because the valid data has not been received.)
interrupt (INTDMA0) occurs when the last received data has been read from the data register. To restart the DMA
transfer, the CSI transfer must be completed.
584
INTDMA0
Because no CSI interrupt is generated when reception starts during CSI master reception, dummy data is written
The received data is automatically transferred from the first byte. (In successive reception mode, the data that is to
A DMA interrupt (INTDMA1) occurs when the last dummy data has been writing to the data register. A DMA
Note The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMAn (INTDMAn), set DSTn to 0 and then DENn to 0 (for details, refer to
15.5.7 Forcible termination by software).
occurs.
DST0 = 0
DEN0 = 0
RETI
Note
Setting for CSI transfer
SIO00 (= SDR00 [7:0])
Write dummy data to
DRA0 = F100H
DBC0 = 0100H
DRA1 = F101H
DBC1 = 00FFH
User program
DMC0 = 06H
DMC1 = 46H
Figure 15-8. Setting Example of CSI Master Reception
DSA0 = 10H
DSA1 = 10H
processing
DEN0 = 1
DEN1 = 1
DST0 = 1
DST1 = 1
Start
End
CHAPTER 15 DMA CONTROLLER
DST1 = 0
User’s Manual U17893EJ8V0UD
DEN1 = 0
RETI
INTCSI00 occurs.
INTDMA1
Note
occurs.
DMA0 transfer CSI reception
DMA1 transfer Writing dummy data
Hardware operation