UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 352

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4.2 Operation in real-time output mode
timer channel 5 as triggers.
pin, but the output value of the ANOn pin up to <5> is undefined. An arbitrary value, however, can be output in <3> by
performing the following settings before performing the setting in <1>.
350
D/A conversion is performed using the interrupt request signals (INTTM04 and INTTM05) of timer channel 4 and
The setting method is described below.
<1> Set the DAMDn bit of the DAM register to 1 (real-time output mode).
<2> Set the analog voltage value to be output to the ANOn pin to the DACSn register.
<3> Set the DACEn bit of the DAM register to 1 (D/A conversion enable).
<4> Operate timer channel 4 and timer channel 5.
<5> D/A conversion starts and the analog voltage set in <2> is output to the ANOn pin when the INTTM04 and
<6> After that, the value set in the DACSn register is output every time the INTTM04 and INTTM05 signals are
D/A conversion starts by setting the DACEn bit, as described in <3>, and an analog voltage is output to the ANOn
i.
ii. Set the voltage value output from the ANOn pin in <3> to the DACSn register.
iii. Afterward, perform <1> to <3>.
Cautions 1. Make the interval for generating a start trigger to the same channel by one clock longer than
Remarks 1. For the output values of the ANO0 and ANO1 pins in the HALT and STOP modes, see CHAPTER 18
Set the DAMDn bit of the DAM register to 0 (normal mode).
Consequently, the value set in ii can be output in <3>. The output level, however, is determined when the
settling time elapses after D/A conversion starts.
Steps <1> to <3> above constitute the initial settings.
INTTM05 signals are generated.
The output level, however, is determined when the settling time elapses after D/A conversion starts.
generated.
Set the analog voltage value to be output to the ANOn pin to the DACSn register before the next D/A
conversion is started (INTTM04 and INTTM05 signals are generated).
When the DACEn bit of the DAM register is set to 0 (D/A conversion operation stop), analog voltage output is
stopped, and the P110/ANO0 and P111/ANO1 pins can be used in port mode. At this time, the P110/ANO0
and P111/ANO1 pins are at high impedance because the PM11n bit of the PM11 register is 1 (input mode).
The set value of the P11 register is output by setting the PM11n bit to 0 (output mode).
2. n = 0, 1
3. f
2. Note the following points in the procedure (i to iii) for outputting an arbitrary value in <3>.
STANDBY FUNCTION.
CLK
f
performed only at the first trigger.
• Do not generate the start trigger of the real-time output mode before enabling D/A
• An arbitrary value cannot be output in <3> if the DACEN bit of the PER0 register is cleared
CLK
conversion operation in <3> after the value is set to the DACSn register in ii.
once after the value is set to the DACSn register in ii.
: CPU/peripheral hardware clock
.
If a start trigger is successively generated for every f
CHAPTER 11 D/A CONVERTER
User’s Manual U17893EJ8V0UD
CLK
, D/A conversion will be