UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 238

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
236
TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAU stop
n = 0 to 7
Sets the TAU0EN bit of the PER0 register to 1.
Sets the TPS0 register.
Sets the TMR0n register (determines operation mode of
channel).
Sets the TIS0n bit to 1 (f
the count clock.
Sets interval (period) value to the TDR0n register.
To use the TO0n output
Sets TOE0n to 1 (only when operation is resumed).
Sets the TS0n bit to 1.
Set values of the TMR0n register, TOM0n, and TOL0n
bits cannot be changed.
Set value of the TDR0n register can be changed.
The TCR0n register can always be read.
The TSR0n register is not used.
Set values of the TO0 and TOE0 registers can be
changed.
The TT0n bit is set to 1.
TOE0n is cleared to 0 and value is set to TO0n bit.
To hold the TO0n pin output level
When holding the TO0n pin output level is not necessary
The TAU0EN bit of the PER0 register is cleared to 0.
Determines clock frequencies of CK00 and CK01.
Clears the TOM0n bit of the TOM0 register to 0 (toggle
mode).
Clears the TOL0n bit to 0.
Sets the TO0n bit and determines default level of the
TO0n output.
Sets TOE0n to 1 and enables operation of TO0n.
Clears the port register and port mode register to 0.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
The TT0n bit automatically returns to 0 because it is a
trigger bit.
Clears TO0n bit to 0 after the value to
be held is set to the port register.
Switches the port mode register to input mode.
Figure 6-38. Operation Procedure of Interval Timer/Square Wave Output Function
Software Operation
SUB
/4) when f
CHAPTER 6 TIMER ARRAY UNIT
SUB
User’s Manual U17893EJ8V0UD
/4 is selected as
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TO0n pin goes into Hi-Z output state.
The TO0n default setting level is output when the port mode
register is in the output mode and the port register is 0.
TO0n does not change because channel stops operating.
The TO0n pin outputs the TO0n set level.
TE0n = 1, and count operation starts.
Counter (TCR0n) counts down. When count value reaches
0000H, the value of TDR0n is loaded to TCR0n again and the
count operation is continued. By detecting TCR0n = 0000H,
INTTM0n is generated and TO0n performs toggle operation.
After that, the above operation is repeated.
TE0n = 0, and count operation stops.
The TO0n pin outputs the TO0n set level.
The TO0n pin output level is held by port function.
The TO0n pin output level goes into Hi-Z output state.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Value of TDR0n is loaded to TCR0n at the count clock
input. INTTM0n is generated and TO0n performs toggle
operation if the MD0n0 bit of the TMR0n register is 1.
TCR0n holds count value and stops.
The TO0n output is not initialized but holds current status.
All circuits are initialized and SFR of each channel is also
initialized.
(The TO0n bit is cleared to 0 and the TO0n pin is set to
port mode.)
Hardware Status