UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 351

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4 Operation of D/A Converter
11.4.1 Operation in normal mode
described below.
D/A conversion is performed using write operation to the DACSn register as the trigger. The setting method is
<1> Set the DAMDn bit of the DAM register to 0 (normal mode).
<2> Set the analog voltage value to be output to the ANOn pin to the DACSn register.
<3> Set the DACEn bit of the DAM register to 1 (D/A conversion enable).
<4> To perform subsequent D/A conversions, write to the DACSn register.
Caution Make the interval for writing DACSn of the same channel by one clock longer than f
Remarks 1. n = 0, 1
Steps <1> and <2> above constitute the initial settings.
D/A conversion starts and the analog voltage set in <2> is output to the ANOn pin when this setting is
performed.
The output level, however, is determined when the settling time elapses after D/A conversion starts.
D/A conversion starts and an analog voltage is output to the ANOn pin when one f
write operation. The output level, however, is determined when the settling time elapses after D/A conversion
starts.
The previous D/A conversion result is held until the next D/A conversion is performed.
When the DACEn bit of the DAM register is set to 0 (D/A conversion operation stop), analog voltage output is
stopped, and the P110/ANO0 and P111/ANO1 pins can be used in port mode. At this time, the P110/ANO0
and P111/ANO1 pins are at high impedance because the PM11n bit of the PM11 register is 1 (input mode).
The set value of the P11 register is output by setting the PM11n bit to 0 (output mode).
is successively performed, only the value written last will be converted.
2. f
CLK
: CPU/peripheral hardware clock
CHAPTER 11 D/A CONVERTER
User’s Manual U17893EJ8V0UD
CLK
clock elapses after the
CLK
. If writing
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