UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 848

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

846
This appendix lists the cautions described in this document.
“Classification (hard/soft)” in the table is as follows.
Hard: Cautions for microcontroller internal/external hardware
Soft: Cautions for software such as register settings or programs
Outline
Pin
functions
Function
RTCCL, RTCDIV Do not enable outputting RTCCL and RTCDIV at the same time.
ANI0/P20 to
ANI7/P27
P40/TOOL0
AV
EV
REGC
P20/ANI0 to
P27/ANI7
P02/SO10/TxD1,
P04/SCK10/
SCL10
P10/SCK00,
P12/SO00/TxD0
REGC
SS
DD
Details of
Function
, EV
, V
DD
SS
, V
SS
Make AV
Make EV
Connect the REGC pin to V
P20/ANI0 to P27/ANI7 are set as analog inputs in the order of P27/ANI7,
P26/ANI6…, P20/ANI0 by the A/D port configuration register (ADPC). When using
P20/ANI0 to P27/ANI7 as analog inputs, start designing from P27/ANI7 (see 10.3 (6)
A/D port configuration register (ADPC) for details).
To use P02/SO10/TxD1 and P04/SCK10/SCL10 as general-purpose ports, set serial
communication operation setting register 02 (SCR02) to the default status (0087H).
In addition, clear port output mode register 0 (POM0) to 00H.
To use P10/SCK00 and P12/SO00/TxD0 as general-purpose ports, set serial
communication operation setting register 00 (SCR00) to the default status (0087H).
ANI0/P20 to ANI7/P27 are set in the digital input (general-purpose port) mode after
release of reset.
The function of the P40/TOOL0 pin varies as described in (a) to (c) below.
In the case of (b) or (c), make the specified connection.
(a) In normal operation mode and when on-chip debugging is disabled (OCDENSET
(b) In normal operation mode and when on-chip debugging is enabled (OCDENSET
(c) When on-chip debug function is used, or in write mode of flash memory
Keep the wiring length as short as possible for the broken-line part in the above
figure.
APPENDIX B LIST OF CAUTIONS
= 0) by an option byte (000C3H)
= 1) by an option byte (000C3H)
programmer
=> Use this pin as a port pin (P40).
=> Connect this pin to EV
=> Use this pin as TOOL0.
level to the pin before reset release.
emulator or a flash memory programmer, or pull it up by connecting it to EV
via an external resistor.
SS
DD
, EV
the same potential as V
User’s Manual U17893EJ8V0UD
SS
the same potential as V
SS
via a capacitor (0.47 to 1
DD
via an external resistor, and always input a high
DD
Directly connect this pin to the on-chip debug
.
Cautions
SS
.
μ
F).
DD
p.20
p.20
p.20
p.20
p.33
p.34
p.34
p.34
p.36
p.41
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