UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 882

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C.1 Major Revisions in This Edition
Remark “Classification” in the above table classifies revisions as follows.
880
Throughout
CHAPTER 1 OUTLINE
p.17
CHAPTER 3 CPU ARCHITECTURE
pp.60 to 64
p.66
CHAPTER 4 PORT FUNCTIONS
p.128
CHAPTER 5 CLOCK GENERATOR
pp.153, 154
p.155
p.163
p.165
p.185
p.186
p.188
p.188
p.191
p.191
p.192
CHAPTER 6 TIMER ARRAY UNIT
p.196
Page
−
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Addition of f
Change of description of AMPH bit in Figure 5-2. Format of Clock Operation Mode Control
Register (CMC)
Change of description of RTCEN bit in Figure 5-7. Format of Peripheral Enable Register (1/2)
Change of Caution 5 in Figure 5-8. Format of Operation Speed Mode Control Register
(OSMC)
Change of description of AMPH bit in Table 5-4. CPU Clock Transition and SFR Register
Setting Examples (1/4) (2) and addition of Remark
Change of description of AMPH bit in Table 5-4. CPU Clock Transition and SFR Register
Setting Examples (2/4) (4) and addition of Remark
Change of (9) CPU clock changing from subsystem clock (D) to high-speed system clock
(C) in Table 5-4. CPU Clock Transition and SFR Register Setting Examples (4/4)
Change of (11) • STOP mode (H) set while CPU is operating with internal high-speed
oscillation clock (B) • STOP mode (I) set while CPU is operating with high-speed system
clock (C) in Table 5-4. CPU Clock Transition and SFR Register Setting Examples (4/4)
Change of Table 5-6. Maximum Time Required for Main System Clock Switchover
Change of Table 5-8. Maximum Number of Clocks Required in Type 2
Change of Table 5-9. Maximum Number of Clocks Required in Type 3 and addition of Remark
Change of Figure 6-1. Block Diagram of Timer Array Unit
Change of status of (A) grade products of the expanded-specification products from under
development to mass production
Change of 1.1 Differences Between Conventional-Specification Products (
Expanded-Specification Products (
Change of Figure 3-7 to Figure 3-11 Correspondence Between Data Memory and
Addressing
Addition of Caution to 3.2.1 (3) Stack pointer (SP)
Change of Figure 4-28. Block Diagram of P110 and P111
MAINC
to Figure 5-1. Block Diagram of Clock Generator and Remark
APPENDIX C REVISION HISTORY
User’s Manual U17893EJ8V0UD
μ
PD78F115xA)
Description
μ
PD78F115x) and
Classification
(b)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(1/5)