UPD78F1152AGC-GAD-AX Renesas Electronics America, UPD78F1152AGC-GAD-AX Datasheet - Page 853

• Manufacturer Part Number: UPD78F1152AGC-GAD-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGC-GAD-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Clock
generator
X1/XT1
oscillator
Clock
generator
operation
when
power
supply
voltage is
turned on
Function
PER0: Peripheral
enable registers
0
OSMC:
Operation speed
mode control
register
HIOTRM:
Internal high-
speed oscillator
trimming register
When LVI
default start
function stopped
is set (option
byte: LVIOFF =
1)
Details of
Function
−
Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power
consumption.
Be sure to clear bit 1 of the PER0 register to 0.
OSMC can be written only once after reset release, by an 8-bit memory manipulation
instruction.
Write “1” to FSEL before the following two operations.
• Changing the clock prior to dividing f
• Operating the DMA controller.
The CPU waits when “1” is written to the FSEL flag.
Interrupt requests issued during a wait will be suspended.
The wait time is 16.6
f
while the CPU is waiting.
To increase f
more clocks have elapsed.
Flash memory can be used at a frequency of 10 MHz or lower if FSEL is 1.
The frequency will vary if the temperature and V
adjustment.
Moreover, if the HIOTRM register is set to any value other than the initial value (10H),
the oscillation accuracy of the internal high-speed oscillation clock may exceed 8
MHz±5%, depending on the subsequent temperature and V
HIOTRM register setting. When the temperature and V
adjustment must be executed regularly or before the frequency accuracy is required.
The
increasing/decreasing the HIOTRM value to a value larger/smaller than a certain
value.
increasing/decreasing the HIOTRM value does not occur.
When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed
by the broken lines in the Figures 5-10 and 5-11 to avoid an adverse effect from
wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a
• Always make the ground point of the oscillator capacitor the same potential as V
• Do not fetch signals from the oscillator.
When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with
XT1, resulting in malfunctioning.
If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application
until the voltage reaches 1.8 V, input a low level to the RESET pin from power
application until the voltage reaches 1.8 V, or set the LVI default start function
stopped by using the option byte (LVIOFF = 0) (see Figure 5-14). By doing so, the
CPU operates with the same timing as <2> and thereafter in Figure 5-13 after reset
release by the RESET pin.
It is not necessary to wait for the oscillation stabilization time when an external clock
input from the EXCLK pin is used.
IH
signal line through which a high fluctuating current flows.
Do not ground the capacitor to a ground pattern through which a high current flows.
/2. However, counting the oscillation stabilization time of f
internal
APPENDIX B LIST OF CAUTIONS
A
User’s Manual U17893EJ8V0UD
CLK
reversal,
high-speed
to 10 MHz or higher, set FSEL to “1”, then change f
μ
s to 18.5
such
oscillation
μ
as
s when f
CLK
the
Cautions
to a clock other than f
CLK
frequency
frequency
= f
IH
DD
, and 33.3
pin voltage change after accuracy
becomes
becoming
DD
voltage change, accuracy
μ
s to 36.9
IH
DD
.
X
voltage change, or
can continue even
faster/slower
slower/faster
CLK
μ
s when f
after two or
CLK
SS
by
by
=
.
p.165
pp.163,
164
p.165
p.165
p.165
p.165
p.166
p.167
p.169
p.170
p.174
p.174
851
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